2012 4th Asia Symposium on Quality Electronic Design (ASQED)最新文献_第3页

Accurate and fast cell spreading for force directed placement 准确和快速的细胞扩散力定向放置

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320470

Sifei Wang, Qiang Zhou, Xu Qian, Yici Cai, Wenchao Gao, Wenjun Zhou

{"title":"Accurate and fast cell spreading for force directed placement","authors":"Sifei Wang, Qiang Zhou, Xu Qian, Yici Cai, Wenchao Gao, Wenjun Zhou","doi":"10.1109/ACQED.2012.6320470","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320470","url":null,"abstract":"As a key phase of force-directed placement, cell spreading can smooth the overlap linearly by adding additional forces to shift cells to the suitable place based on the utilization of bins. However, the magnitude and direction of these additional forces is hard to be determined. Unreasonable additional forces will bring great damage to the wire length and run time. In this paper, we present a new fast and accurate cell spreading technique called FACS to cope with these problems and further optimize wire length. It mainly takes the following measures: Firstly, cells are grouped into three steady sets according to their attributes, external connections and last move, and the different strategies of amending force are adopted base on the sets respectively. Secondly, the barrier is added during the cell spreading, which will limit the maximum step length and avoid breaking the integrity of original placement. This makes the average wire length reduced by 0.84%. Thirdly, the magnitude of half perimeter wire length (HPWL) change has also been put into additional forces function to amend the deviation which caused by quadratic wire length model. The experimental results show that the average wire length can be reduced by 12%.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128233157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal and optical analysis of multi-chip LED packages with different electrical connection and driving current 不同电连接和驱动电流的多芯片LED封装的热光学分析

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320507

Ming Yeng Lim, Sik Hong Gan, S. Lee, Z. Lee, M. Devarajan

引用次数: 5

Analyzing BTI effects on retention registers 分析BTI对保留率的影响

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320478

Yao-Te Wang, Ing-Chao Lin

引用次数: 0

Phosphor concentration effects on the thermal and optical performance of cool and warm white single chip LEDs 荧光粉浓度对冷白光和暖白光单芯片led热学和光学性能的影响

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320502

Hwang Hsien Shiung, A. Permal, M. Devarajan

引用次数: 4

Fabrication and characterization of silicon-based Ba0.7Sr0.3TiO3 thin films for FeFET applications FeFET用硅基Ba0.7Sr0.3TiO3薄膜的制备与表征

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320498

A. Saif, P. Poopalan

引用次数: 0

Parasitic capacitance and density optimization modeling fill synthesis for VLSI interconnect 超大规模集成电路互连的寄生电容和密度优化建模填充综合

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320469

Joel Yeo Yee Kiat, K. Nyunt, Wong Hin Yong

{"title":"Parasitic capacitance and density optimization modeling fill synthesis for VLSI interconnect","authors":"Joel Yeo Yee Kiat, K. Nyunt, Wong Hin Yong","doi":"10.1109/ACQED.2012.6320469","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320469","url":null,"abstract":"In transition to ultra deep sub-micron (UDSM) design technology nodes, fill synthesis solutions have increasingly caused performance impacts to the interconnect design, due to the parasitic capacitances induced by the dummy fill structures. Meeting chemical mechanical polishing (CMP) density design rules alone is no longer sufficient. Large spacing setbacks between functional interconnects and dummy fill structures are commonly used to minimize the parasitic capacitance. However, as designs scale further into the nanometer range, a huge percentage of metal densities are sacrificed and achieving minimum density requirements in certain areas is not feasible. In this paper, an innovative fill synthesis solution is proposed to optimize both the requirements between parasitic capacitance reduction and the improved density requirements. First, we develop various experimentation models on a 65nm layout topology to examine the capacitance behavior. From the experimentation, we propose a capacitance and density optimization modeling (OM) fill synthesis for lateral metal layers to increase the global CMP density up to ~80%, reduce the total capacitance by ~50% to preserve the interconnect capacitance and achieve much faster computation TPT (Throughput Time) as compared with traditional fill flows.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121459430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

System management with relational database for mask tape-out 系统管理用关系型数据库进行掩模带出

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320488

Ng Chow Leng, A. Har, Ow Yong Wai Tat

引用次数: 1

Retention time characterization and optimization of logic-compatible embedded DRAM cells 逻辑兼容嵌入式DRAM单元的保留时间表征和优化

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320471

A. Do, H. Yi, K. Yeo, T. T. Kim

引用次数: 6

3D IC implementation for MPSOC architectures: Mesh and butterfly based NoC MPSOC架构的3D IC实现:基于网格和蝴蝶的NoC

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320492

O. Hammami, A. M'zah, M. H. Jabbar, D. Houzet

引用次数: 12

A novel hardware implementation for the IEEE 802.22 Turbo-Like Interleaver IEEE 802.22类涡轮交织器的一种新型硬件实现

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320505

M. Ahmadi, A. Azarpeyvand, S. M. Fakhraie, R. Asadpour

引用次数: 0