2012 4th Asia Symposium on Quality Electronic Design (ASQED)最新文献_第4页

A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications 一个单调和低功耗的数字控制振荡器，使用标准电池的SoC应用

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320487

D. Sheng, Ching-Che Chung, Jhih-Ci Lan

引用次数: 5

Unified model for analyzing timing delay and crosstalk effects in Carbon Nanotube interconnects 碳纳米管互连中时序延迟和串扰效应的统一分析模型

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320484

Debaprasad Das, H. Rahaman

引用次数: 7

Enhanced tracing and visibility in logic emulation environment by optimized design slicing 通过优化设计切片，增强了逻辑仿真环境的跟踪和可见性

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320500

S. Banerjee, T. Gupta

{"title":"Enhanced tracing and visibility in logic emulation environment by optimized design slicing","authors":"S. Banerjee, T. Gupta","doi":"10.1109/ACQED.2012.6320500","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320500","url":null,"abstract":"Field Programmable Gate Array (FPGA) based logic emulators, used for functional verification of large and complex System-on-chip (SoC) designs are characterized by two conflicting requirements - execution speed and signal visibility. Achieving 100% signal visibility in post-processing debug for long emulation runs impacts execution speed and requires large amount of disk space. Techniques like combinational reconstruction, periodic snapshot based tracing, state restoration etc. have reduced the amount of trace data and hence the impact on execution speed to some extent, but fail to provide a scalable solution for growing design sizes. Selective tracing based on signal list specification does not guarantee tracing all relevant signals needed to be investigated to debug a functional mismatch, often requiring re-runs to generate relevant data. This paper presents a novel tracing and visibility system based on the concept of optimized design slicing (ODS), which minimizes trace data while providing sufficient debug visibility by tracing only a set of design portions or “slices” that are likely to affect values of a set of “observed variables”, or in other words influence a set of properties under verification. These slices are extracted automatically from the design logic and capture all the signals likely to impact the observed variables, ensuring sufficient debug visibility. The slices are “optimized” by techniques like software memory replay and blackbox elimination. The proposed system achieves effective reduction in trace data, higher execution speed and provides necessary debug visibility for post-processing debug.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121093645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces 基于高速接口异步协议的波管道串行反序列化器的设计

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320513

Bui Chinh Hien, Seok-Man Kim, Kyoungrok Cho

引用次数: 8

Load model technique for mesh-structured power distribution network 网格结构配电网负荷模型技术

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320504

Hyoeon Yang, T. Bae, Jinwook Kim, Young Hwan Kim

引用次数: 2

Monte Carlo simulation in VDDmin modeling across Fab process VDDmin跨Fab过程建模中的蒙特卡罗仿真

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320499

Huiping Guo, Yang Yang, Jiang Bowen

引用次数: 0

A methodology for LBIST logic diagnosis in high volume manufacturing 大批量生产中LBIST逻辑诊断方法研究

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320510

A. Jayalakshmi, Tan Ewe Cheong

{"title":"A methodology for LBIST logic diagnosis in high volume manufacturing","authors":"A. Jayalakshmi, Tan Ewe Cheong","doi":"10.1109/ACQED.2012.6320510","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320510","url":null,"abstract":"LBIST (Logic Built-In Self Test) is a structural test method that tests a circuit by running test patterns generated on the die as opposed to ATPG (Automatic Test Pattern Generation) method in which the test patterns are pre-generated to test specific fault types. LBIST has emerged as an alternative scan based test methodology due to its attractive benefits such as reduced pattern size and field testability. LBIST uses pseudo random patterns enabling it to generate patterns on the die saving tester memory to a large extent. At the same time it poses challenges to enable fail data collection for later debug as the LBIST test iterations are usually large (typically 100000). Tester time is not a big concern for a LBIST based method if the objective is to know if the unit passed or failed, but memory usage is a concern due to the need to compare intermediate scan responses to determine and collect failing responses for diagnosis and debug purposes. This motivated us to come up with a methodology for fail data collection that optimizes tester time and memory and collects enough fail data to provide acceptable diagnosis quality. In this paper we have presented a methodology for fail data collection and discussed the tester overheads for LBIST logic diagnosis.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122650797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A GA-based optimization for Fourth-order Sallen-Key low-pass filter 基于遗传算法的四阶萨伦键低通滤波器优化

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320494

Teoh Yeong Yeap, N. Chin

引用次数: 1

Maximization of SRAM energy efficiency utilizing MTCMOS technology 最大化SRAM能源效率利用MTCMOS技术

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320472

Bo Wang, Jun Zhou, T. T. Kim

引用次数: 13

Process variation tolerant SRAM cell design using additive model considering NBTI effect 考虑NBTI效应的可加性模型的过程公差SRAM单元设计

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320474

A. Khosropour, S. Kashani-Gharavi, R. Asadpour, A. Afzali-Kusha

{"title":"Process variation tolerant SRAM cell design using additive model considering NBTI effect","authors":"A. Khosropour, S. Kashani-Gharavi, R. Asadpour, A. Afzali-Kusha","doi":"10.1109/ACQED.2012.6320474","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320474","url":null,"abstract":"In this paper, we propose a statistical methodology for the design of process variation tolerant yet low-power 6T SRAM cells. In addition to process variations, Negative Bias Temperature Instability (NBTI) has been included in the design methodology such that the time dependence of the failure probability is taken into account. To increase the modeling accuracy of the statistical distributions of different SRAM reliability metrics such as static noise margin (SNM) and Read Current, a modeling scheme based on nonlinear regression is suggested. The design technique, which minimizes the failure probabilities due to the process variations, considers the widths and lengths of the six transistors of the cell as design parameters. The sizes of the transistors are selected such that the area constraint is not violated. Also, to include the static power consumption of the SRAM block in the design methodology, we introduce a method for estimating the SRAM block leakage distribution. To show the efficacy of the technique, the results of applying this methodology for a 45 nm CMOS technology are presented.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2