{"title":"网格结构配电网负荷模型技术","authors":"Hyoeon Yang, T. Bae, Jinwook Kim, Young Hwan Kim","doi":"10.1109/ACQED.2012.6320504","DOIUrl":null,"url":null,"abstract":"This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than 0.0207 V (1.4%) and 0.0048 V (0.325%) respectively.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Load model technique for mesh-structured power distribution network\",\"authors\":\"Hyoeon Yang, T. Bae, Jinwook Kim, Young Hwan Kim\",\"doi\":\"10.1109/ACQED.2012.6320504\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than 0.0207 V (1.4%) and 0.0048 V (0.325%) respectively.\",\"PeriodicalId\":161858,\"journal\":{\"name\":\"2012 4th Asia Symposium on Quality Electronic Design (ASQED)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 4th Asia Symposium on Quality Electronic Design (ASQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACQED.2012.6320504\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACQED.2012.6320504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Load model technique for mesh-structured power distribution network
This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than 0.0207 V (1.4%) and 0.0048 V (0.325%) respectively.
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