Monte Carlo simulation in VDDmin modeling across Fab process

Abstract

VDDmin is defined as the lowest supply voltage at which a device can produce correct logic states. It is typically obtained by performing a binary or linear supply voltage search. VDDmin or very-low voltage (VLV) testing is a non-IDDQ defect based test method that has been shown to be an effective method to screen manufacturing defects [1, 2, 3, 4]. It is taken as an indicator of device performance and reliability. Monte Carlo simulation is a random sampling based computational methodology, used extensively for engineering analysis [5, 6, 7]. This paper discuss a VDDmin determination methodology base on-Monte Carlo simulation, case study is presented to illustrate that this approach can precisely predict yield impact due to process shift.