Parasitic capacitance and density optimization modeling fill synthesis for VLSI interconnect

In transition to ultra deep sub-micron (UDSM) design technology nodes, fill synthesis solutions have increasingly caused performance impacts to the interconnect design, due to the parasitic capacitances induced by the dummy fill structures. Meeting chemical mechanical polishing (CMP) density design rules alone is no longer sufficient. Large spacing setbacks between functional interconnects and dummy fill structures are commonly used to minimize the parasitic capacitance. However, as designs scale further into the nanometer range, a huge percentage of metal densities are sacrificed and achieving minimum density requirements in certain areas is not feasible. In this paper, an innovative fill synthesis solution is proposed to optimize both the requirements between parasitic capacitance reduction and the improved density requirements. First, we develop various experimentation models on a 65nm layout topology to examine the capacitance behavior. From the experimentation, we propose a capacitance and density optimization modeling (OM) fill synthesis for lateral metal layers to increase the global CMP density up to ~80%, reduce the total capacitance by ~50% to preserve the interconnect capacitance and achieve much faster computation TPT (Throughput Time) as compared with traditional fill flows.