Soft-error hardened redundant triggered latch

Abstract

This paper presents a soft error hardened latch suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes, external logic, as well as the pulse generator circuit. The hardening method is based on redundancy to protect internal nodes and filter out transients resulted from combinational logic. It also uses redundant clocking technique which results in more robustness. The circuit is designed in 90nm CMOS technology and simulated with the HSPICE. Simulation results indicate its lower-power and -delay, and ability to recover from single particle strike on internal and clock nodes, and input transient tolerance up to 120ps.