Low-power and robust SRAM cells based on asymmetric FinFET structures

Abstract

In this paper, we investigate the characteristics of low-power and robust SRAM cells based on asymmetric FinFET structures in a 32 nm technology. They are based on asymmetric source and drain structures and include Asymmetric Drain Spacer Extension (ADSE) and Asymmetric Doped Drain (ADD) FinFETs. The study includes two recently introduced 6-T SRAM cells based on these structures. In addition, we propose four transistor driverless (4-TDL) and loadless (4-TLL) SRAM cells based on these asymmetric structures. In the investigation, which compares the structures, the effect of different channel orientations is also considered. The results indicate that for 6-T, 4-TDL, and 4-TLL with different channel orientations asymmetric structures have higher read stabilities than the symmetric ones. In addition, the channel orientation (100) presents a higher read stability for 4-TLL while the channel orientation (110) gives rise to a better read stability for 6-T and 4-TDL. Asymmetric structures, however, have lower read currents where the ADSE structure leads to the least one. In terms of write operation, the asymmetric structures present better stability where 4-T cells outperform the 6-T cell. Finally, the results on static power shows that the ADD FinFET structure provides the lowest static power values due to a better DIBL control.