{"title":"带双通孔插入的多电压岛型x时钟树结构的电源感知","authors":"Chia-Chun Tsai, Trong-Yen Lee","doi":"10.1109/ACQED.2012.6320495","DOIUrl":null,"url":null,"abstract":"This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power. The delay effect due to total number of vias is also accounted. Experimental results show that X-clock tree based on multi-voltage islands has 22.46% and 5.41% respectively in power and delay less than that of single voltage island.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Power awareness for multi-voltage island X-clock tree construction with double-via insertion\",\"authors\":\"Chia-Chun Tsai, Trong-Yen Lee\",\"doi\":\"10.1109/ACQED.2012.6320495\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power. The delay effect due to total number of vias is also accounted. Experimental results show that X-clock tree based on multi-voltage islands has 22.46% and 5.41% respectively in power and delay less than that of single voltage island.\",\"PeriodicalId\":161858,\"journal\":{\"name\":\"2012 4th Asia Symposium on Quality Electronic Design (ASQED)\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 4th Asia Symposium on Quality Electronic Design (ASQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACQED.2012.6320495\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACQED.2012.6320495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power awareness for multi-voltage island X-clock tree construction with double-via insertion
This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power. The delay effect due to total number of vias is also accounted. Experimental results show that X-clock tree based on multi-voltage islands has 22.46% and 5.41% respectively in power and delay less than that of single voltage island.