Decoupling capacitor placer algorithm with routing and area consideration in VLSI layout design

Abstract

Conventional manual placement for decoupling capacitance (decap) is very time consuming and may lead to unavoidable human errors. In VLSI design environments there is a critical need to have an automated way via CAD tools, particularly to ensure quick turn-around times in the face of strong time-to-market pressures. Unfortunately, existing placer algorithms work best on rectangle placement regions, but are less efficient when working on polygon placement regions with more than 4 vertices. Therefore, in this paper, we present and propose a decap placer using new placement algorithm named Size and Level oriented algorithm (SL). This decap placer is implemented with routing and area consideration which works efficiently on not only rectangle but polygon placement regions as well. Furthermore, different placement orientations are implemented also in this decap placer for better decaps placement coverage.