2023 IEEE International Reliability Physics Symposium (IRPS)最新文献_第8页

Impact of Barrier Metal Thickness on SRAM Reliability 阻挡金属厚度对SRAM可靠性的影响

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118344

R. Ranjan, P. R. Perepa, Ki-Don Lee, Hokyung Park, Peter Kim, G. Yerubandi, J. Haefner, Caleb Dongkyun Kwon, M. Jin, Wenhao Zhou, H. Shim, Shin-Young Chung

{"title":"Impact of Barrier Metal Thickness on SRAM Reliability","authors":"R. Ranjan, P. R. Perepa, Ki-Don Lee, Hokyung Park, Peter Kim, G. Yerubandi, J. Haefner, Caleb Dongkyun Kwon, M. Jin, Wenhao Zhou, H. Shim, Shin-Young Chung","doi":"10.1109/IRPS48203.2023.10118344","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118344","url":null,"abstract":"To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ($tau_{mathrm{c}}/tau_{mathrm{e}}$, or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $mathbf{RTN}downarrow$, bias temperature instability (BTI) $mathbf{recovery}uparrow$, SRAM SNM $mathbf{shift}downarrow$) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance Technology Nodes 先进技术节点电路退化的统一老化模型框架捕获装置

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117914

S. Mukhopadhyay, C. Chen, M. Jamil, Jihan Standfest, I. Meric, B. Gill, S. Ramey

引用次数: 0

Signatures of Positive Gate Over-Drive Induced Hole Trap Generation and its Impact on p-GaN Gate Stack Instability in AlGaN/GaN HEMTs AlGaN/GaN hemt中正栅极过驱动诱导空穴阱产生的特征及其对p-GaN栅极堆叠不稳定性的影响

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117793

R. Malik, Vipin Joshi, R. R. Chaudhuri, Mehak Ashraf Mir, Zubear Khan, Avinas N. Shaji, Madhura Bhattacharya, Anup T. Vitthal, M. Shrivastava

引用次数: 2

Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling 基于有限元模型的晶圆级芯片封装失效模式预测

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117636

Viktor Dudash, K. Machani, B. Boehme, S. Capecchi, Jungtae Ok, K. Meier, F. Kuechenmeister, M. Wieland, K. Bock

{"title":"Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling","authors":"Viktor Dudash, K. Machani, B. Boehme, S. Capecchi, Jungtae Ok, K. Meier, F. Kuechenmeister, M. Wieland, K. Bock","doi":"10.1109/IRPS48203.2023.10117636","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117636","url":null,"abstract":"In this study a Finite Element Model (FEM) was designed in order to predict the reliability behavior of 7×7 mm2 Wafer Level Chip Scale Packages (WLCSP) during board level thermal cycling tests, considering different solder material models for SAC405 and SACQ interconnects. A significant difference in plastic strains within the package was observed for a variety of solder material models: Compared to SACQ interconnects an approximate 70% plastic strain increase in solder and a 35% plastic strain reduction in the polyimide passivation layer was observed for packages with SAC405 interconnects. Simulations were verified by experimental thermal cycling test data done at board level. During thermal cycling, packages showed different failure modes depending on the interconnect material used in the package. Also, SAC405 showed earlier failure. Maximum strain obtained from simulations was used as an indicator of potential failure locations for the solder alloy and polyimide layer. The proposed model setup enables precise simulation results, which are well aligned with the actual experimental findings on the behavior of WLCSP with SAC405 and SACQ interconnects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130482077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Recent Advances on Electromigration in Cu/SiO2 to Cu/SiO2 Hybrid Bonds for 3D Integrated Circuits 三维集成电路中Cu/SiO2到Cu/SiO2杂化键的电迁移研究进展

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118173

S. Moreau, D. Bouchu, J. Jourdon, B. Ayoub, S. Lhostis, H. Frémont, P. Lamontagne

引用次数: 1

Classification of Commercial SiC-MOSFETs Based on Time-Dependent Gate-current Characteristics 基于时变门电流特性的商用sic - mosfet分类

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117833

E. Murakami, T. Takeshita, K. Oda, M. Kobayashi, K. Asayama, M. Okamoto

引用次数: 0

Modeling of NBTI Induced Threshold Voltage Shift Based on Activation Energy Maps Under Consideration of Variability 考虑可变性的基于激活能映射的NBTI诱导阈值电压偏移建模

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117818

C. Bogner, C. Schlünder, M. Waltl, H. Reisinger, T. Grasser

{"title":"Modeling of NBTI Induced Threshold Voltage Shift Based on Activation Energy Maps Under Consideration of Variability","authors":"C. Bogner, C. Schlünder, M. Waltl, H. Reisinger, T. Grasser","doi":"10.1109/IRPS48203.2023.10117818","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117818","url":null,"abstract":"One of the major challenges for modeling BTI degradation in modern technology nodes and deeply scaled transistors is the occurrence of significant time dependent variability (TDV). This means that due to the sparsity of defects, the impact of single defects as well as variation in the number of defects per device need to be taken into consideration. We present a modeling approach based on physical principles to describe both mean parameter degradation as well as TDV. Our approach is based on activation energy maps combined with an exponential-Poisson model in order to capture variability. For parameter extraction a combination of ultra fast measurements on large area transistors and transistor array measurements are applied. Thereby, ultra fast measurements have the capability to make a wide range of capture-/emission times experimentally accessible, improving the confidence of the extracted activation energy map. On the other hand, transistor arrays have proven to be the ideal test vehicle to efficiently measure an ensemble of transistors and to asses TDV.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET 符合工艺和环境温度变化的可靠纳米片场效应管自热感知阈值电压调制

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10117918

Sunil Rathore, Rajeewa Kumar Jaisawal, P. Kondekar, N. Gandhi, Shashank Banchhor, Young Suh Song, N. Bagga

{"title":"Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET","authors":"Sunil Rathore, Rajeewa Kumar Jaisawal, P. Kondekar, N. Gandhi, Shashank Banchhor, Young Suh Song, N. Bagga","doi":"10.1109/IRPS48203.2023.10117918","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117918","url":null,"abstract":"Internal and external process variations severely affect the device threshold voltage $(mathrm{V}_{text{th}})$ and, in turn, the device's reliability. For the first time, this paper presented a thorough analysis of the self-heating aware $mathrm{V}_{text{th}}$ variation of a Nanosheet FET and, thus, the device's aging. Using well-calibrated TCAD models, we evaluated the 'change in $V_{th} ^{prime}$ and performed an extensive design space exploration to analyze: (i) the impact of work function (WF) modulation owing to metal grain sizes and effective grains (for confined dimensions) on $mathrm{V}_{text{th}}$ variation; (ii) the impact of ambient temperature (TA) on $mathrm{V}_{text{th}}$ variation; (iii) the influence of trap charges on device characteristics; (iv) how the consideration of RDF impacted $mathrm{V}_{text{th}};$ (v) the device's aging, i.e., end of a lifetime (EOL). These investigations provided guidelines for designing a reliable Nanosheet FET (NSFET) to investigate and mitigate early aging.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115241653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness 单片三维集成BEOL双端口铁电场效应管，打破记忆窗口和铁电厚度之间的权衡

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118286

Om. Prakash, K. Ni, H. Amrouch

引用次数: 2

Static, Dynamic, and Short-circuit Characteristics of Split-Gate 1.2 kV 4H-SiC MOSFETs 分栅1.2 kV 4H-SiC mosfet的静态、动态和短路特性

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI: 10.1109/IRPS48203.2023.10118091

Dongyoung Kim, Skylar DeBoer, Stephen A. Mancini, S. Isukapati, Justin Lynch, Nick Yun, Adam J. Morgan, S. Jang, Woongje Sung

{"title":"Static, Dynamic, and Short-circuit Characteristics of Split-Gate 1.2 kV 4H-SiC MOSFETs","authors":"Dongyoung Kim, Skylar DeBoer, Stephen A. Mancini, S. Isukapati, Justin Lynch, Nick Yun, Adam J. Morgan, S. Jang, Woongje Sung","doi":"10.1109/IRPS48203.2023.10118091","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118091","url":null,"abstract":"This paper reports static, dynamic, and short-circuit characteristics of split-gate (SG) 1.2 kV 4H-SiC MOSFETs. Conventional (C) MOSFETs and SG-MOSFETs were fabricated and evaluated. Identical conduction behaviors were achieved due to them having the same cell pitch. Although the maximum electric field in the gate oxide is higher in the SG-MOSFETs, this both device architectures obtained similar breakdown voltages with low leakage current. Due to the structure of the split-gate, the reverse capacitance $(mathbf{C}_{mathbf{rss}})$ was reduced by 32 % when compared to conventional MOSFETs. As a result, switching loss for turn-on and turn-off transients was reduced, and thus total switching loss was reduced by 25 % in the SG- M OSFE Ts. Finally, the short-circuit (SC) ruggedness of the MOSFETs were evaluated. Even though the maximum drain current is higher in the SG-MOSFETs, under SC condition, a similar short-circuit withstand time (SCWT) was obtained. In order to further investigate short-circuit characteristics, non-isothermal simulations were conducted. It was discovered that there is no issue with the exposed edge of the gate in SG- M OSFE Ts under SC conditions despite the high electric field in gate oxide. Significantly reduced energy loss was achieved in the SG-MOSFETs with no compromise in static and short-circuit characteristics compared to the conventional MOSFETs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115807854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1