A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance Technology Nodes

Abstract

Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design Technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a single transistor as well as by the reliability performance of the overall IP/product. Although the IP/Product reliability evaluation is most beneficial at the early stages of the technology development, it is often very expensive, and no certain aging model methodology exists to quantify the risks. In this work, for the first time we demonstrate a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits. Various Ring-Oscillators (RO) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions. Such consistent framework helps to guide the process technology development, as well as provides for high-confidence product/IP reliability design assurance.