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IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.最新文献

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Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping 缓冲俘获对氮化镓场效应管脉冲I-V曲线和电流崩塌影响的数值分析
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 2005-12-01 DOI: 10.1109/CSICS.2005.1531789
H. Nakano, H. Takayanagi, K. Yonemoto, K. Horio
{"title":"Numerical analysis of pulsed I-V curves and current collapse in GaN FETs as affected by buffer trapping","authors":"H. Nakano, H. Takayanagi, K. Yonemoto, K. Horio","doi":"10.1109/CSICS.2005.1531789","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531789","url":null,"abstract":"Two-dimensional transient analysis of GaN MESFETs is performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves are derived from the transient characteristics, and are compared with the steady-state I-V curves. It is shown that so-called current collapse or current reduction is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. It is suggested that to minimize current collapse in GaN-based FETs, an acceptor density in a semi-insulating GaN layer should be made low, although the current cutoff behaviour may be degraded.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115461844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
300 GHz InP DHBT large signal model including current blocking effect and validated by Gilbert multiplier circuits 包含电流阻塞效应的300 GHz InP DHBT大信号模型，并经吉尔伯特乘法器电路验证
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 2005-12-01 DOI: 10.1109/CSICS.2005.1531758
J. Lai, D. Caruth, Y. Chuang, K. Cimino, R. Elder, D. Jansen, F. Stroili, M. Le, M. Feng
{"title":"300 GHz InP DHBT large signal model including current blocking effect and validated by Gilbert multiplier circuits","authors":"J. Lai, D. Caruth, Y. Chuang, K. Cimino, R. Elder, D. Jansen, F. Stroili, M. Le, M. Feng","doi":"10.1109/CSICS.2005.1531758","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531758","url":null,"abstract":"This paper describes a modeling approach for Vitesse VIP2 300 GHz InP/InGaAs DHBT technology, including the nonlinear effects in base-collector region covering current blocking, velocity modulation and self-heating. Model is verified in terms of single devices and integrated circuits. Good model fitting to measured DC and S-parameters data from single HBTs is achieved, and several circuits based on Gilbert multiplier are designed for the purposes of model validation and high-speed applications. Nonlinear properties of these circuits are measured and compared with the simulation results from different bipolar transistor models. The variable gain amplifier reported in this paper achieves the highest gain-bandwidth product of over 520 GHz under the limitation of measurement capability.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127562902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Improved efficiency, IP3-bandwidth and robustness of a microwave Darlington amplifier using 0.5/spl mu/m ED PHEMT and a new circuit topology 采用0.5/spl mu/m ED PHEMT和新的电路拓扑，提高了微波达林顿放大器的效率、ip3带宽和鲁棒性
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531769
K. Kobayashi
{"title":"Improved efficiency, IP3-bandwidth and robustness of a microwave Darlington amplifier using 0.5/spl mu/m ED PHEMT and a new circuit topology","authors":"K. Kobayashi","doi":"10.1109/CSICS.2005.1531769","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531769","url":null,"abstract":"This paper reports on the first results of a self-biased e-mode PHEMT Darlington amplifier. The e-mode PHEMTs enable a FET Darlington implementation while a new Darlington active bias topology reduces bias variation over temperature and supply, and improves overall efficiency by reducing supply operation. A 3.3V-75mA amplifier achieves a BW of 0.1-14GHz, 12.3dB gain, NF of 3.5dB, IP3 and P1dB of 33.1dBm and 16dBm @ 2GHz, respectively. A 5V-75mA amplifier achieves a 0.1-10 GHz BW, 20.2 dB gain, NF of 2.9 dB, IP3 and P1dB of 34.2dBm and 21.8dBm @ 2 GHz, respectively. The new PHEMT Darlington amplifier design enables a factor of 2 better IP3-bandwidth product and lower voltage operation capability compared to InGaP-based Darlington amplifiers.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Trusted foundry: the path to advanced SiGe technology 可信赖的代工厂:通往先进SiGe技术的道路
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531738
G. Carlson
{"title":"Trusted foundry: the path to advanced SiGe technology","authors":"G. Carlson","doi":"10.1109/CSICS.2005.1531738","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531738","url":null,"abstract":"The trusted foundry program offers a path for government agencies and their contractors to design and fabricate circuits in IBM's stateside facilities that assure against loss of confidentiality. This paper will outline the method of engaging with IBM on a trusted foundry program and then describe the advanced technologies and services offered to government agencies under the IBM trusted foundry agreement, focusing on silicon germanium capabilities.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High dynamic range multibit /spl Sigma//spl Delta/ ADC based receiver prototype employing dynamic error correction 采用动态纠错的高动态范围多比特/spl Sigma//spl Delta/ ADC接收机原型
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1576600
L. E. Pellon
{"title":"High dynamic range multibit /spl Sigma//spl Delta/ ADC based receiver prototype employing dynamic error correction","authors":"L. E. Pellon","doi":"10.1109/CSICS.2005.1576600","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1576600","url":null,"abstract":"In this paper, dynamic performance results are presented on a prototype multibit Σ∆ band-pass Analog to Digital Converter (ADC), implemented for conversion of intermediate frequency (IF) input signals to digital base band I/Q samples. The results include “real-time” processed outputs that exhibits high dynamic range over programmable output bandwidths ranging from 2.5 MHz to 20 MHz, centered at an IF input frequency of 70MHz. This prototype represents the first in a series of receiver developments employing this tunable Σ∆ ADC topology, focused on 100 dB SNR and 100 dB multitone SFDR performance levels. The architecture employs a band-pass multibit Σ∆ modulator and a digital processor that includes nonlinearity error correction, digital down conversion and decimation filtering.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scalability of SOI CMOS technology and circuit to millimeter wave performance SOI CMOS技术和电路对毫米波性能的可扩展性
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531780
J. Plouchart, J. Kim, J. Gross, R. Trzcinski, K. Wu
{"title":"Scalability of SOI CMOS technology and circuit to millimeter wave performance","authors":"J. Plouchart, J. Kim, J. Gross, R. Trzcinski, K. Wu","doi":"10.1109/CSICS.2005.1531780","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531780","url":null,"abstract":"This paper presents the high-frequency performance of the 130 and 90-nm SOI technologies as well as its integration capabilities and scalability. With a measured 303-GHz Ft, 1.6-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26-GHz the SOI NMOS transistors exhibits performances ahead of the ITRS roadmap. Passives are integrated in the microprocessor back-end, and the 1.8fF//spl mu/m/sup 2/ capacitance density of the vertical native capacitor (VNCAP) in a 90nm SOI CMOS improves by 28%, as compared to a 120 nm SOI CMOS. In the circuit design section, we will show how this high-level of performance will expand the use of CMOS to high-performance millimeter-wave applications with examples of such circuits for frequency generation, and amplification.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128148053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Up to 80-Gbit/s operations of 1:4 demultiplexer IC with InP HBTs 最高80gbit /s的操作1:4解复用IC与InP HBTs
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531834
K. Sano, H. Fukuyama, K. Murata, K. Kurishima, N. Kashio, T. Enoki, H. Sugahara
{"title":"Up to 80-Gbit/s operations of 1:4 demultiplexer IC with InP HBTs","authors":"K. Sano, H. Fukuyama, K. Murata, K. Kurishima, N. Kashio, T. Enoki, H. Sugahara","doi":"10.1109/CSICS.2005.1531834","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531834","url":null,"abstract":"We report up to 80-Gbit/s operations of a 1:4 demultiplexer (DMX) IC with InP HBTs of f/sub T/=292 GHz, f/sub max/=308 GHz. The circuit features are 1) the multiphase clock (MPC) architecture to suppress the increase of the power consumption, and 2) the high collector current density of 5.0 mA//spl mu/m/sup 2/ for the fastest circuit blocks. To measure the IC at over 50 Gbit/s where available data pulse pattern generators (PPGs) are few, we constructed two-types of data PPGs, which were a purely electrical PPG (E-PPG) and an optoelectronic PPG (OE-PPG). With these technologies, we successfully confirmed the operations up to 80 Gbit/s for the 1:4 DMX IC.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"11 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the road to ESD safe GaAs HBT MMICs 在通往ESD安全GaAs HBT mmic的道路上
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531838
Yintat Ma, G. Li
{"title":"On the road to ESD safe GaAs HBT MMICs","authors":"Yintat Ma, G. Li","doi":"10.1109/CSICS.2005.1531838","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531838","url":null,"abstract":"In order to design a robust electrostatic discharge (ESD) protected microwave monolithic integrated circuits (MMICs) in GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events is presented. The results include not only the intrinsic HBT's ESD robustness performance but also its dependence on device layout, ballast resistor and process. Low capacitance loading ESD protection circuits for power and broadband amplifiers are also introduced to further improve the MMICs' ESD robustness along with examples.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The wide and the narrow: DARPA/MTO programs for RF applications in wide bandgap and antimonide-based semiconductors 宽和窄:DARPA/MTO计划用于宽带隙和锑基半导体中的射频应用
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531739
M. Rosker
{"title":"The wide and the narrow: DARPA/MTO programs for RF applications in wide bandgap and antimonide-based semiconductors","authors":"M. Rosker","doi":"10.1109/CSICS.2005.1531739","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531739","url":null,"abstract":"This paper discusses two DARPA/MTO III-V semiconductor material development programs, the wide bandgap semiconductor for RF applications (WBGS-RF) program and the antimonide-based compound semiconductor (ABCS) program. For WBGS-RF, results are detailed from the recently-completed phase I effort with a focus on semi-insulating substrates and epitaxial growth. Also detailed are the goals and early progress report from phase II of WBGS-RF. Near the end, summarized are results achieved in the recently-completed ABCS program.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A low phase noise InGaP-GaAs HBT transformer power combining VCO 结合压控振荡器的低相位噪声InGaP-GaAs HBT变压器电源
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531766
P. Lai, S. Long
{"title":"A low phase noise InGaP-GaAs HBT transformer power combining VCO","authors":"P. Lai, S. Long","doi":"10.1109/CSICS.2005.1531766","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531766","url":null,"abstract":"A transformer-based power combining technique is shown to be an efficient method for reducing oscillator phase noise. Higher signal power can be achieved while avoiding breakdown without penalty in tuning range. An InGaP-GaAs HBT process was used to fabricate the 1GHz VCO. The measured phase noise at 100 KHz, 1 MHz and 3 MHz offset frequency is -116, -136 and -145dBc/Hz respectively. The VCO dissipates 3mW.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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