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IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.最新文献

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MMIC-oscillator designs for ultra low phase noise 超低相位噪声的mmic振荡器设计
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531813
H. Zirath, H. Jacobsson, M. Bao, M. Ferndahl, R. Kozhuharov
{"title":"MMIC-oscillator designs for ultra low phase noise","authors":"H. Zirath, H. Jacobsson, M. Bao, M. Ferndahl, R. Kozhuharov","doi":"10.1109/CSICS.2005.1531813","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531813","url":null,"abstract":"Various balanced VCO-topologies like cross-connected (negative gm), coupled cross-connected, coupled Colpitt and Clapp oscillators, all with a fully integrated tank are reported. In this study, different MMIC/RFIC technologies such as SiGe HBT, InGaP-GaAs-HBT, PHEMT, MHEMT, and CMOS are represented and parameters such as phase-noise, output power, dc-power consumption, and tuning range are compared. All oscillators are designed for low phase noise. Low phase noise can be achieved by CMOS, PHEMT and MHEMT technologies although SiGe and InGaP-GaAs HBT based oscillators have demonstrated the lowest phase noise. Both fundamental and second harmonic VCOs are represented in the evaluation.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology 用于短距离数据通信的电气和光学收发器，采用VLSI 90纳米体和SOI CMOS技术制造
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531805
T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss, P. Buchmann, C. Berger, M. Schmatz
{"title":"Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology","authors":"T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss, P. Buchmann, C. Berger, M. Schmatz","doi":"10.1109/CSICS.2005.1531805","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531805","url":null,"abstract":"This paper presents a comprehensive overview on our recent high-speed high-density links designs in 90-nm bulk and SOI CMOS. A 12.5 GByte/s link macro is described. The macro consists of 10 channels at 12.5 Gb/s each. For very short links, i.e. on multi chip modules (MCM), a 20 Gb/s PAM4 transmitter and receiver is presented. Longer links can be realized by a low-power 4/spl times/10 Gb/s optical extension, also fabricated in CMOS.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133819081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel 50-Gbit/s NRZ-RZ converter with retiming function using InP HEMT technology 采用InP HEMT技术设计了一种具有重定时功能的50gbit /s NRZ-RZ变换器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531749
T. Suzuki, Y. Kawano, Y. Nakasha, T. Takahashi, K. Makiyama, T. Hirose
{"title":"A novel 50-Gbit/s NRZ-RZ converter with retiming function using InP HEMT technology","authors":"T. Suzuki, Y. Kawano, Y. Nakasha, T. Takahashi, K. Makiyama, T. Hirose","doi":"10.1109/CSICS.2005.1531749","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531749","url":null,"abstract":"We developed a novel electrical non-return-to-zero (NRZ) to return-to-zero (RZ) converter circuit based on a master-slave D-type flip-flop (D-FF). Its decision and re-timing function makes the converter without any delay or phase control circuitry, which are usually employed to adjust the phase alignment of data and clock. The circuit achieved 50-Gbit/s operation by using 0.13 /spl mu/m gate-length InP HEMT technology. The supply voltage was -5.2 V and the power consumption was 1.1W. A module with the circuit mounted realized 44-Gbit/s operation.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The state-of-the-art of silicon-on-sapphire CMOS RF switches 最先进的蓝宝石上硅CMOS射频开关
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531812
Dylan Kelly, Chris Brindle, Clint Kemerling, Mike Stuber
{"title":"The state-of-the-art of silicon-on-sapphire CMOS RF switches","authors":"Dylan Kelly, Chris Brindle, Clint Kemerling, Mike Stuber","doi":"10.1109/CSICS.2005.1531812","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531812","url":null,"abstract":"Silicon-on-Sapphire (SOS) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulating sapphire substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOS FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOS FETs can be stacked in series to withstand high voltages when biased in subthreshold. This work studies the tradeoffs of SOS RF switch design and compares SOS against other technologies such as GaAs and Si-based SOI. Also presented is a high power SP6T switch with insertion loss of 0.6 dB at 2 GHz and isolation of 40 dB at 2 GHz. The presented switch has the highest linearity reported to date of any SP6T switch with a P1dB of 20 W and OIP3 of <+70 dBm.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131811448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
Ka-band MMIC high power amplifier (4W at 30GHz) with record compact size ka波段MMIC高功率放大器(4W在30GHz)，具有创纪录的紧凑尺寸
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531822
K. Kong, B. Nguyen, S. Nayak, M. Kao
{"title":"Ka-band MMIC high power amplifier (4W at 30GHz) with record compact size","authors":"K. Kong, B. Nguyen, S. Nayak, M. Kao","doi":"10.1109/CSICS.2005.1531822","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531822","url":null,"abstract":"We report a compact and efficient Ka-band high power amplifier with output power of over 4W at 30GHz and record compact area of 8.63mm/sup 2/ in a Ka-band high power amplifier (HPA) class. The bias capacitors (/spl sim/80pF) are included inside the MMIC so that it reduces the assembly cost in the package or module. We employed a dual-recessed 0.15/spl mu/m power pHEMT production process and 2mil-substrate technology to achieve high output power with high efficiency and compact design. The output power (CW measurement) is 36.2dBm, and, the gain, 22.5dB, at 30GHz. These results set the benchmark of CW output power per millimeter square area for the reported performance of Ka-band HPA MMICs.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A low power 10 Gb/s serial link transmitter in 90-nm CMOS 低功耗10gb /s串行链路发射器在90纳米CMOS
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531807
A. Rylyakov, Sergey V. Rylov
{"title":"A low power 10 Gb/s serial link transmitter in 90-nm CMOS","authors":"A. Rylyakov, Sergey V. Rylov","doi":"10.1109/CSICS.2005.1531807","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531807","url":null,"abstract":"A 10Gb/s half-rate serial link differential transmitter is optimized for low power and features a 4:1 multiplexer and a 4-tap feed-forward equalizer. The chip is error-free at 10Gb/s (231-1 PRBS) and 125/spl deg/C, driving an AC-coupled 100 Ohm differential load with a 0.9V peak-to-peak differential (ppd) signal and consuming a total of 174mW (80mA from a 1.65V supply in the output driver section and 35mA from 1.2V in the multiplexer section).","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
High-speed InP-based Mach-Zehnder modulators for telecom applications 电信应用的高速inp - Mach-Zehnder调制器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531745
H. Yasaka, K. Tsuzuki, N. Kikuchi, E. Yamada, Y. Shibata, T. Ishibashi
{"title":"High-speed InP-based Mach-Zehnder modulators for telecom applications","authors":"H. Yasaka, K. Tsuzuki, N. Kikuchi, E. Yamada, Y. Shibata, T. Ishibashi","doi":"10.1109/CSICS.2005.1531745","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531745","url":null,"abstract":"A novel InP-Based traveling-wave electrode Mach-Zehnder modulator has been proposed and fabricated. It has an n-i-n isotype heterostructure to reduce both electrical signal loss and optical loss caused by p-type cladding layer. We obtained error-free operation for a 40-Gbit/s NRZ signal in a push-pull configuration with a very low driving voltage of 1.3 V/sub pp/. We also confirmed that the modulator has low chirp characteristics by demonstrating a 100-km SMF transmission with a penalty of less than 1.5 dB for a 10-Gbit/s NRZ signal.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Collector optimization in advanced SiGe HBT technologies 先进SiGe HBT技术中的收集器优化
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531779
Q.Z. Liu, B. Orner, L. Lanzerotti, M. Dahlstrom, W. Hodge, M. Gordon, J. Johnson, M. Gautsch, J. Greco, J. Rascoe, D. Ahlgren, A. Joseph, J. Dunn
{"title":"Collector optimization in advanced SiGe HBT technologies","authors":"Q.Z. Liu, B. Orner, L. Lanzerotti, M. Dahlstrom, W. Hodge, M. Gordon, J. Johnson, M. Gautsch, J. Greco, J. Rascoe, D. Ahlgren, A. Joseph, J. Dunn","doi":"10.1109/CSICS.2005.1531779","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531779","url":null,"abstract":"With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128503996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier 一个5位，18 GS/秒SiGe HBT跟踪保持放大器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531774
X. Li, W. Kuo, Y. Lu, R. Krithivasan, J. Cressler, A. Joseph
{"title":"A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier","authors":"X. Li, W. Kuo, Y. Lu, R. Krithivasan, J. Cressler, A. Joseph","doi":"10.1109/CSICS.2005.1531774","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531774","url":null,"abstract":"An ultra-high-speed track-and-hold amplifier (THA) using a switched-emitter-follower (SEF) configuration is presented. Implemented in a commercially-available 0.18 /spl mu/m 120 GHz SiGe HBT BiCMOS technology, the THA core occupies a compact area of only 120 /spl times/ 200 /spl mu/m/sup 2/. The THA can operate at a sampling rate of 18 GS/sec with a total harmonic distortion (THD) of -32.3 dBc, and dissipates 128 mW, significantly smaller than other THAs in the literature operating at similar sampling rates.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130002454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
An InP-based OEIC for optical arbitrary waveform generation 一种基于inp的光学任意波形生成OEIC
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1576601
A. Leven, J. Lin, P. Kondratko, U. Koc, J. Lee, Y. Baeyens, Y. Chen
{"title":"An InP-based OEIC for optical arbitrary waveform generation","authors":"A. Leven, J. Lin, P. Kondratko, U. Koc, J. Lee, Y. Baeyens, Y. Chen","doi":"10.1109/CSICS.2005.1576601","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1576601","url":null,"abstract":"We demonstrate a 4-bit 12.5 GSample/s optical arbitrary waveform generator (OAWG) based on an InP photonic integrated circuit and a low phase-noise mode-locked laser. A single-tone spurious-free dynamic range (SFDR) of 32 dB was obtained.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124277095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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