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IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.最新文献

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110-GHz static frequency divider in SiGe bipolar technology SiGe双极技术中的110 ghz静态分频器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1576599
S. Trotta, H. Knapp, T. Meister, K. Aufinger, J. Bock, W. Simburger, A. Scholtz
{"title":"110-GHz static frequency divider in SiGe bipolar technology","authors":"S. Trotta, H. Knapp, T. Meister, K. Aufinger, J. Bock, W. Simburger, A. Scholtz","doi":"10.1109/CSICS.2005.1576599","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1576599","url":null,"abstract":"We present a static frequency divider designed in a 225 GHz fT SiGe bipolar technology. The divider has a divide ratio of four and it is operational from 200 MHz up to 110 GHz (limited by the measurement equipment). At a -5.2 V power supply, the circuit, including the two dividers and the input and output stages, consumes less than 260 mA. Index Terms SiGe, Static Frequency Divider","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131314141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A X-band 4-bit mHEMT phase shifter 一个x波段4位mHEMT移相器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531754
A. Khalil, M. Mahfoudi, F. Traut, M. Shifrin, J. Chavez
{"title":"A X-band 4-bit mHEMT phase shifter","authors":"A. Khalil, M. Mahfoudi, F. Traut, M. Shifrin, J. Chavez","doi":"10.1109/CSICS.2005.1531754","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531754","url":null,"abstract":"A 4-bit X-band phase shifter is developed using 0.15/spl mu/m mHEMT technology. The mHEMT technology has an (Ron . Coff) = 0.25 pS, minimizing the switch insertion loss. Three different bit topologies are used to achieve both first pass success and best possible performance. The phase shifter operates between 8-12 GHz with 5.5 dB mean insertion loss, +/- 0.7 dB amplitude error, less than 5/spl deg/ RMS phase error, and better than 10 dB return losses. The die area is 1.7 mm/sup 2/.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123941057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
50% PAE WCDMA basestation amplifier implemented with GaN HFETs 用GaN hfet实现的50% PAE WCDMA基站放大器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531768
{"title":"50% PAE WCDMA basestation amplifier implemented with GaN HFETs","authors":"","doi":"10.1109/CSICS.2005.1531768","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531768","url":null,"abstract":"A high performance GaN HFET WCDMA basestation power amplifier is presented, which uses an envelope tracking bias system to achieve high linearity and efficiency. The measured overall power-added efficiency (PAE) reached 50.7%, with a normalized power RMS error of 0.7% and ACLR of -52dBc at an offset frequency of 5MHz, at an average output power of 37.2W and gain of 10.0dB for a single carrier WCDMA signal. To the authors' knowledge, this corresponds to the best efficiency reported for a single stage base station power amplifier. Digital predistortion (DPD) was used at two levels: memoryless DPD to compensate for the expected gain variation of the amplifier over the bias envelope trajectory, and deterministic memory mitigation, to further improve the linearity. The signal envelope had a peak-to-average power ratio of 7.67dB.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128634447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A frequency agile 40 Gb/s half rate linear phase detector for data jitter measurement 用于数据抖动测量的40 Gb/s半速率线性鉴相器
IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. Pub Date : 1900-01-01 DOI: 10.1109/CSICS.2005.1531747
R. Karlquist, T. Marshall, R. Tuyl, C. Hutchinson
{"title":"A frequency agile 40 Gb/s half rate linear phase detector for data jitter measurement","authors":"R. Karlquist, T. Marshall, R. Tuyl, C. Hutchinson","doi":"10.1109/CSICS.2005.1531747","DOIUrl":"https://doi.org/10.1109/CSICS.2005.1531747","url":null,"abstract":"A 40 Gb/s half-rate linear phase detector IC for NRZ data, implemented in a 200 GHz f/sub T/, InP DHBT process, with a novel architecture, is described. The IC can be used for clock recovery or jitter measurement. The new architecture has less critical internal timing, and better speed and linearity than previous phase detectors. Half rate operation doubles the allowable propagation delay. Dual outputs alternate in time and combine linearly, allowing overlap without error, resulting in greater linear range. Operation at any rate is possible because no rate-specific delay lines are used. The intrinsic jitter for a 40 Gb/s 2/sup 31/-1 PRBS pattern is 50 mUl pk-pk in a 320 MHz bandwidth.","PeriodicalId":149955,"journal":{"name":"IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121746092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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