High dynamic range multibit /spl Sigma//spl Delta/ ADC based receiver prototype employing dynamic error correction

In this paper, dynamic performance results are presented on a prototype multibit Σ∆ band-pass Analog to Digital Converter (ADC), implemented for conversion of intermediate frequency (IF) input signals to digital base band I/Q samples. The results include “real-time” processed outputs that exhibits high dynamic range over programmable output bandwidths ranging from 2.5 MHz to 20 MHz, centered at an IF input frequency of 70MHz. This prototype represents the first in a series of receiver developments employing this tunable Σ∆ ADC topology, focused on 100 dB SNR and 100 dB multitone SFDR performance levels. The architecture employs a band-pass multibit Σ∆ modulator and a digital processor that includes nonlinearity error correction, digital down conversion and decimation filtering.