2021 IEEE International Test Conference (ITC)最新文献

{"title":"Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory","authors":"M. Mayahinia, Christopher Münch, M. Tahoori","doi":"10.1109/ITC50571.2021.00036","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00036","url":null,"abstract":"Computation in Memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114987399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SymbA: Symbolic Execution at C-level for Hardware Trojan Activation","authors":"Arash Vafaei, Nick Hooten, M. Tehranipoor, Farimah Farahmandi","doi":"10.1109/ITC50571.2021.00031","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00031","url":null,"abstract":"Due to the global supply of semiconductor intellectual property (IP) cores, modern system-on-chip (SoC) designs are vulnerable to malicious functionality, referred to as hardware Trojans. Hardware Trojans are inserted to bypass the security mechanisms in a SOC or cause confidentiality, integrity, and availability violations. There is an increased emphasis on finding effective solutions to generate tests to activate Trojans in hardware designs (if any) in third party IPs. However, state-of-the-art approaches suffer from ineffectiveness in detection and scalability. In this paper, we propose SymbA that utilizes symbolic execution at C/C++ level to activate malicious functionality hidden in RTL designs. SymbA is based on mapping of RTL design to C level and leveraging the existing powerful software-level symbolic execution engine to generate tests. SymbA maps back the generated tests to RTL and checks if the hidden Trojans have been activated. In this paper, we use KLEE Symbolic Execution Engine and show the efficiency of SymbA by applying it to a number of Trust-Hub benchmarks. SymbA improves the existing state-of-the-art techniques significantly with regard to performance, coverage and memory usage.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115326088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Functional In-Field Self-Test for Deep Learning Accelerators","authors":"Yi He, T. Uezono, Yanjing Li","doi":"10.1109/ITC50571.2021.00017","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00017","url":null,"abstract":"We present a technique that generates high-quality functional in-field self-tests specifically targeting deep learning (DL) accelerators. These functional tests can be applied in the field during normal operation of a DL accelerator, which is crucial to ensure that the safety and/or reliability requirements are met for any given application, including safety-critical applications such as self-driving cars, robotics, and more.Our technique takes advantage of special architectural characteristics and application properties to achieve high functional test coverage while incurring minimal system-level costs. Moreover, we devise different strategies for the compute units (which support computation operations) and the control units (which control data movement) because these two types of units exhibit different properties. For the compute units of a DL accelerator, we first use combinational ATPG to generate test patterns with high test coverage, which is possible because these units do not contain complex sequential logic. Next, we map the ATPG patterns to one or more equivalent deep neural networks (DNNs) that can be directly executed on the accelerator, which is possible given the well-defined dataflow/reuse algorithm of a DL accelerator. For the control units, we leverage the property that typically only one or a few fixed DNNs are deployed at a time in many application domains (e.g., self-driving cars). Thus, it is sufficient to target only the faults that can directly affect the correctness of the DNNs that are currently deployed. This is done by executing different layers of each target DNN using carefully-crafted input and weight values to maximize test coverage while minimizing test time.We apply our technique using Nvidia’s open-source accelerator as a case study to demonstrate its efficacy. Our results show that our technique achieves high test coverage. For the compute units, 99.9% single stuck-at functional test coverage is achieved. For the control units, we are able to prove that, given any target DNN, 100% coverage can be achieved for a large class of single and multiple fault models. The in-field functional self-test time is also very low, < 17 ms for various representative DNNs. These functional tests can be applied during boot-up, reset, and even concurrently with normal operation by executing DNN test programs directly on the accelerator, without requiring any test support in the hardware.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123342503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits","authors":"T. Melis, E. Simeu, L. Saury, E. Auvray","doi":"10.1109/ITC50571.2021.00033","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00033","url":null,"abstract":"Finding critical nodes and devices inside a circuit is important to have a reliable and safe circuit. It is also a necessary information to successfully solve a failure analysis. Besides, this is a difficult task when dealing with analog and mixed signal circuits for safety applications. For complex designs, the list of signals that influences a selected output is not easy to be deduced. This paper proposes a solution to meet these needs. It is a method that is potentially opened to a broader application domain than failure analysis. The obtained results are encouraging and show the advantages of such approach.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123411539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning","authors":"Hanbin Hu, Chen-Yu He, Peng Li","doi":"10.1109/ITC50571.2021.00019","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00019","url":null,"abstract":"Wafer map pattern recognition is instrumental for detecting systemic manufacturing process issues. However, high cost in labeling wafer patterns renders it impossible to leverage large amounts of valuable unlabeled data in conventional machine learning based wafer map pattern prediction. We proposed a contrastive learning framework for semi-supervised learning and prediction of wafer map patterns. Our framework incorporates an encoder to learn good representation for wafer maps in an unsupervised manner, and a supervised head to recognize wafer map patterns. In particular, contrastive learning is applied for the unsupervised encoder representation learning supported by augmented data generated by different transformations (views) of wafer maps. We identified a set of transformations to effectively generate similar variants of each original pattern. We further proposed a novel rotation-twist transformation to augment wafer map data by rotating each given wafer map for which the angle of rotation is a smooth function of the radius. Experimental results demonstrate that the proposed semi-supervised learning framework greatly improves recognition accuracy compared to traditional supervised methods, and the rotation-twist transformation further enhances the recognition accuracy in both semi-supervised and supervised tasks.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation","authors":"Franziska Mayer, Christian Schott, Enrico Billich, Saeid Yazdani, U. Heinkel, Georg Daler, B. Ruf, Ricardo Pannuzzo, W. Dickenscheid","doi":"10.1109/ITC50571.2021.00053","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00053","url":null,"abstract":"Modern semiconductor mixed-signal products such as fully integrated circuits become more and more complex. This results in an increasing effort to develop the corresponding test programs for semiconductor test systems. Every implementation error in the test program could have a huge impact to the customer and must be avoided by all means. Therefore, the verification of the test program is an essential part of the development and the resulting effort has been increased significantly over the last years.Our methodology aims to formalize the test program verification, automate its execution, and evaluate the outcome. A high number of test sets containing multiple tests are created by using an approach based on mutation testing. Device responses provided to the test program are specified and the obtained results are compared against expected ones. Variants of correct and defective response sets can be emulated without the need for a physical or modeled device with the same characteristics. As the verification runs in tester offline mode, neither a semiconductor test system nor physical devices are required to run this approach.The concept is demonstrated by executing a given test program providing a special subset for device responses and assessing the obtained test program results.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126866066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation","authors":"C. Bartsch, Stephan Wilhelm, Daniel Kästner, D. Stoffel, W. Kunz","doi":"10.1109/ITC50571.2021.00057","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00057","url":null,"abstract":"Resilience against hardware faults is a major concern for safety-critical embedded systems which has been addressed in several standards. These standards demand a systematic and thorough safety evaluation, especially for the highest safety levels. In order to provide the data for this evaluation, we propose a scalable and formal approach to fault propagation analysis for hardware/software systems. We consider soft errors by single event upsets (SEUs) which corrupt data in hardware registers and examine their effect on the high-level software. Our method identifies all faults of a given fault list that can have an effect on selected objects of the high-level software, such as the specified safety functions, and gives formal guarantees for other faults that do not do any harm.Scalability of our approach results from combining an analysis at the binary and hardware level with an analysis of the high-level source code using Abstract Interpretation. The result is a mapping between a fault in the hardware and affected locations in the source code. Effectiveness and scalability of this method are demonstrated on an industry-oriented software system with about 138 k lines of C code.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs","authors":"J. Corso, Saidapet Ramesh, K. Abishek, Ley Teng Tan, Chik Hooi Lew","doi":"10.1109/ITC50571.2021.00037","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00037","url":null,"abstract":"After a continued analysis of more than a year to reduce DPPB on NXP automotive designs, it was observed that some subtle at-speed defects were not getting screened out using combination of traditional Stuck-At, Transition-Delay and Small-Delay-Defect based ATPG patterns. Traditional delay fault models for automatic test pattern generation target a single transition that propagates to the output(s) of a gate. Single Transition-Delay model finds the stimulus that can sensitize a transition on a port that, in presence of a delay defect, will result in the capture of incorrect state. Failure Analysis data confirmed that multiple transitions on inputs changed the timing of the outputs in a different way than a single transition, in the presence of subtle defect mechanisms in certain library cells. Multiple Input Switching (MIS) is a known STA modeling problem that can affect the timing of a gate under various conditions of load, slew, and temporal distance of signals at the inputs. In this paper, we present a new ATPG fault model that complements the traditional transition delay models and, a method to identify the stimuli required to expose these kinds of defects. The new patterns were first validated on the tester, resulting in proof of concept of new methodology. Later, at-speed Multi-Transition Fault Model (MTFM) ATPG patterns were released for multiple NXP AUTO designs and high-volume yield data from more than 9 million units confirmed unique fallout of at least 0.5ppm from the new MTFM topoff patterns. Also, MTFM based input stimuli comparison was done on limited set of library cells between MTFM and traditional Cell-Aware 2 Time-Frame UDFM based patterns. It was confirmed that only MTFM patterns produced the required multi-transitions through the inputs of the targeted cell instances in multiple designs.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115551598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums","authors":"Ching-Yuan Chen, K. Chakrabarty","doi":"10.1109/ITC50571.2021.00016","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00016","url":null,"abstract":"Deep learning (DL) applications are becoming in- creasingly ubiquitous. However, recent research has highlighted a number of reliability concerns associated with deep neural networks (DNNs) used for DL. In particular, hardware-level reliability of DNNs is of concern when DL models are mapped to specialized neuromorphic hardware such as memristor-based crossbars. Faults in the crossbars can deviate the corresponding DNN model weights from their trained values. It is therefore desirable to have an on-device \"checksum\" function to indicate if model weights are deviated. We present a backdooring technique that fine-tunes DNN weights to implement the checksum function. The backdoored checksum function is triggered only when inferencing is carried out using a special set of data points with watermarks. We show that backdooring, i.e., fine-tuning of DNN weights, has no impact on the inferencing accuracy of the original DNN model. Moreover, the implemented checksum functions for AlexNet and VGG-16 remarkably outperform baseline approaches. Based on the proposed on-line functional testing solution, we present a computing framework that can efficiently recover the inferencing accuracy of a memristor-mapped DNN from weight deviations. Compared to related recent work, the proposed framework achieves 5.6 × speed-up in time-to-recovery and reduces the on-chip test data volume by 99.99%.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designs","authors":"F. A. D. Silva, A. Bagbaba, S. Hamdioui, C. Sauer","doi":"10.1109/ITC50571.2021.00047","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00047","url":null,"abstract":"The current demands for developing safe automotive applications require extensive analysis and evaluation of potential random hardware faults. In general, part of this analysis is manually performed by experts, resulting in an expensive, time-consuming, and error-prone process. This paper proposes an automated approach to classify faults overlooked by traditional methods. Our methodology deploys code coverage and formal to identify nodes that do not disrupt safety-critical functionalities, enabling the classification of additional faults. The approach is validated based on an Automotive CPU, according to ISO 26262 guidelines. The results show an improvement in Diagnostic Coverage of 1.15%, increasing the Single Point Fault Metric (SPFM) to 97.3%, enabling ASIL C compliance without any hardware redundancy.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"6 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116116404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}