Shahram Rasoolzadeh, Aein Rezaei Shahmirzadi, A. Moradi
{"title":"Impeccable Circuits III","authors":"Shahram Rasoolzadeh, Aein Rezaei Shahmirzadi, A. Moradi","doi":"10.1109/ITC50571.2021.00024","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00024","url":null,"abstract":"As a recent fault-injection attack, SIFA defeats most of the known countermeasures. Although error-correcting codes have been shown effective against SIFA, they mainly require a large redundancy to correct a few bits. In this work, we propose a hybrid construction with the ability to detect and correct injected faults at the same time. We provide a general implementation methodology which guarantees the correction of up to tc-bit faults and the detection of at most td faulty bits. Exhaustive evaluation of our constructions, by the open-source fault diagnostic tool VerFI, indicate the success of our designs in achieving the desired goals.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126896678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels","authors":"Chenwei Liu, Qiaoyue Tang","doi":"10.1109/ITC50571.2021.00028","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00028","url":null,"abstract":"Wafer Bin Maps (WBM) frequently show various spatial failure patterns that provide crucial information for engineers to identify the root cause of failures and their consequent low yield. To shorten the root-cause diagnosis process, it is important to classify different failure patterns with high accuracy, especially when there is mixed type of failure patterns on the same wafer. The main challenges of mixed type classification in WBMs include: 1) Lack of accurately annotated real-world training dataset, 2) Imbalanced/long-tail distributions among classes, 3) Synthesized training data usually cannot reflect the practical application conditions. In this paper, we propose a weakly supervised learning approach and use an ensemble method based on triplet CNN models to classify mixed-type failure patterns in WBMs. We train the models based on the public WM-811K dataset, which is collected from real products but with only single-label annotations. We demonstrate that such models could mitigate the imbalanced class distribution and being able to learn efficiently from a weakly labeled dataset and achieve superior performances on the classification of real wafer maps with long-tail distributed mixed type failures. We also discuss the practical considerations of implementing such models and the advantages of using triplet over binary CNN models.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123173072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Brain-Inspired Computing for Wafer Map Defect Pattern Classification","authors":"P. Genssler, H. Amrouch","doi":"10.1109/ITC50571.2021.00020","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00020","url":null,"abstract":"Brain-Inspired hyperdimensional computing is a quickly emerging alternative machine-learning concept. Hypervectors with thousands of dimensions represent real-world data. Thanks to this redundancy, the system becomes robust against noise in the input data, but also resilient against faults, similar to the human brain. The light-weight operations with hypervectors are fully parallelizable enabling fast learning and inference at the edge. A classifier achieving high accuracies can be created through one-shot learning from few examples. Such a feature is particularly valuable in the area of semiconductor testing, where the number of training samples, especially for cutting-edge technology, is limited. In this work, we explore the applicability of brain-inspired hyperdimensional computing to the field of testing for the first time. With the example of wafer map defect pattern classification, we investigate the challenges and opportunities of this emerging concept.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131347297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accessing general IEEE Std. 1687 networks via functional ports","authors":"E. Larsson, P. Murali, Ziling Zhang","doi":"10.1109/ITC50571.2021.00051","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00051","url":null,"abstract":"Reconfigurable scan networks (RSNs), like IEEE Std. 1687 networks, offer flexible and scalable access to embedded (on-chip) instruments. These networks are typically accessed from the outside via a dedicated test port, like the test access port (TAP) of IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, the IEEE Std. P1687.1 working group is exploring how existing functional ports can be used. Fundamental challenges are to determine what hardware to include in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We have previously shown hardware and protocol to access a limited type of IEEE Std. 1687 networks, known as flat segment insertion bit (SIB)-based networks. In this paper, we present a solution to handle general IEEE Std. 1687 networks. We have made a number of implementations with various benchmarks on an FPGA to evaluate the data overhead and the area usage.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi Sun, Hui Jiang, L. Ramakrishnan, Jennifer Dworak, Kundan Nepal, T. Manikas, R. I. Bahar
{"title":"Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits","authors":"Yi Sun, Hui Jiang, L. Ramakrishnan, Jennifer Dworak, Kundan Nepal, T. Manikas, R. I. Bahar","doi":"10.1109/ITC50571.2021.00045","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00045","url":null,"abstract":"Excessive test power can cause multiple issues at manufacturing as well as during field test. To reduce both shift and capture power during test, we propose a DFT-based approach where we split the scan chains into segments and use extra control bits inserted between the segments to determine whether a particular segment will capture. A significant advantage of this approach is that a standard ATPG tool is capable of automatically generating the appropriate values for the control bits in the test patterns. This is true not only for stuck-at fault test sets, but for Launch-off-Capture (LOC) transition tests as well. It eliminates the need for expensive post processing or modification of the ATPG tool. Up to 37% power reduction can be achieved for a stuck-at test set while up to 35% reduction can be achieved for a transition test set for the circuits studied.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"19 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125916227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testability-Enhancing Resynthesis of Reconfigurable Scan Networks","authors":"N. Lylina, Chih-Hao Wang, H. Wunderlich","doi":"10.1109/ITC50571.2021.00009","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00009","url":null,"abstract":"Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected.In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127623207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Shang, M. Shinohara, Eiji Kato, M. Hashimoto, J. Kiljan
{"title":"Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry","authors":"Y. Shang, M. Shinohara, Eiji Kato, M. Hashimoto, J. Kiljan","doi":"10.1109/ITC50571.2021.00032","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00032","url":null,"abstract":"Time-domain reflectometry (TDR) that employs electro-optical sampling affords excellent resolution at the femtosecond level and exhibits a comprehensible impulse waveform, thereby allowing quick defect identification in a single trace. However, it remains challenging to identify a defect in a trace of multiple branches; the TDR waveform is complex. Generally, the TDR waveform of a defective unit features defect-dependent reflection (DDR) and defect-independent reflection (DIR). DDR is contributed by a branch with the defect; DIR is contributed by the remaining good branches. The DDR (not the DIR) is required to analyze the defect; however, the DIR tends to overwhelm the waveform, rendering interpretation difficult. In this work, we use an open-short normalization (OSN) method to eliminate the DIR. The resulting DDR immediately identifies the defect location and type. The OSN method was verified using both simulation and measurements.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130447055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies","authors":"Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, A. Kuwana, K. Hatayama, Haruo Kobayashi","doi":"10.1109/ITC50571.2021.00038","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00038","url":null,"abstract":"This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4Kpoint data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency, a specified resolution of the ADC under test and a given number of FFT points (data samples) in the incoherent sampling environment. Mature technology combinations with their optimal usage and without advanced methods can lead to the low-cost high-quality testing of the ADC, which can be well accepted in industry. Their analysis, simulation and experimental results are shown.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131497915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles","authors":"C. Amarnath, Md Imran Momtaz, A. Chatterjee","doi":"10.1109/ITC50571.2021.00055","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00055","url":null,"abstract":"Autonomous systems that rely on multiple interacting subsystems require a high degree of reliability and resilience to a wide range of failures in those subsystems. In this work the effects of electro-mechanical failures in the steer-by-wire, brake-by-wire and vehicle controller subsystems of autonomous vehicles on subsystem and vehicle level performance are studied. A machine learning assisted correction approach using Gaussian Processes to learn fault dynamics on-line is developed and its efficacy is demonstrated under a variety of vehicle maneuvers and failure conditions at the subsystem and vehicle levels.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130617620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaohui Cui
{"title":"The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack","authors":"Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaohui Cui","doi":"10.1109/ITC50571.2021.00014","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00014","url":null,"abstract":"The physical unclonable function (PUF) against the modeling attack is of great concern in recent years, since the modeling attack has been proved to be a serious security threat to the PUF circuits. The double-layer PUF was reported as a PUF scheme to resist the fully connected artificial neural network based modeling attack, and its test chip was fabricated and tested. This work proposes an artificial neural network (ANN) based modeling method according to the working principle of the target PUF, and successfully attacks the double-layer PUF. To enhance the anti-modeling-attack capability of the double-layer PUF, the address swapping, the XORing, and the dimensional extension techniques are proposed. The attack results show that the prediction accuracy of the proposed ANN-based model with the proposed techniques drops obviously. And the prediction accuracy is about 50.04% if all the three proposed techniques are applied in combination. It manifests that the proposed security enhancement techniques are able to improve the resilience of the double-layer PUF against the modeling attacks effectively. Both the randomness and uniqueness of the improved doublelayer PUFs are approximate to the ideal value (50%), and the reliability of the improved PUFs remain unchanged compared with the original counterpart because the operations on the resistive random memory (RRAM) array are the same.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121883293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}