2021 IEEE International Test Conference (ITC)最新文献

MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification 用于晶圆图分类的微型交互式偏移网络(MINIONs)

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00027

Y. Zeng, Li-C. Wang, Chuanhe Jay Shan

引用次数: 2

Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement 基于自适应神经网络的成品率容积诊断根本原因分析

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00010

Xin Huang, Min Qin, Ruosheng Xu, Cheng Chen, Shangling Jui, Zhihao Ding, Pengyun Li, Yu Huang

{"title":"Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement","authors":"Xin Huang, Min Qin, Ruosheng Xu, Cheng Chen, Shangling Jui, Zhihao Ding, Pengyun Li, Yu Huang","doi":"10.1109/ITC50571.2021.00010","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00010","url":null,"abstract":"Root Cause Analysis (RCA) is a critical technology for yield improvement in integrated circuit manufacture. Traditional RCA prefers unsupervised algorithms such as Expectation Maximization based on Bayesian models. However, these methods are severely limited by the weak predictive capability of statistical models and can’t effectively transfer the yield learning experience from old designs and processes to the new ones. Motivated by recent advancements of deep learning, in this paper we propose a Neural-Network-based adaptive framework for RCA in yield improvement. The proposed framework consists of an inference module and a self-adaptive module. The former receives volume diagnosis reports and predicts the root cause distributions. The latter is able to adapt the inference module to new designs and processes based on a few of targeted samples without any manual adjustment. Experimental results show that a relatively large improvement on accuracy is achieved by the proposed framework on simulated diagnosis data. Furthermore, the transferring capability of the self-adaptive module is also validated by the results.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125677077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators 使用功能路径环振荡器的性能监视器的可扩展设计流程

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00041

T. Kilian, H. Ahrens, Daniel Tille, M. Huch, Ulf Schlichtmann

引用次数: 4

AAA: Automated, On-ATE AI Debug of Scan Chain Failures AAA:自动，On-ATE AI扫描链故障调试

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00044

Chris Nigh, Gaurav Bhargava, R. D. Blanton

引用次数: 2

Testability-Aware Low Power Controller Design with Evolutionary Learning 基于进化学习的可测试性低功耗控制器设计

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00046

Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu

引用次数: 0

On Reduction of Deterministic Test Pattern Sets 确定性测试模式集的约简

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00035

Stephan Eggersglüß, Sylwester Milewski, J. Rajski, J. Tyszer

引用次数: 8

Machine Learning for Circuit Aging Estimation under Workload Dependency 负载依赖下电路老化估计的机器学习

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00011

F. Klemme, H. Amrouch

{"title":"Machine Learning for Circuit Aging Estimation under Workload Dependency","authors":"F. Klemme, H. Amrouch","doi":"10.1109/ITC50571.2021.00011","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00011","url":null,"abstract":"Circuit analysis with respect to aging-induced degradation is critical to ensure correct operation throughout the entire lifetime of a chip. However, state-of-the-art techniques only allow for the consideration of uniformly applied degradation, despite the fact that different workloads will lead to different degradations due to the different induced activities. This imposes over-pessimism in estimating the required timing guardbands, resulting in unnecessary losses of performance and efficiency. In this work, we propose an approach that takes real-world workload dependencies into account and generates workload-specific aging-aware standard cell libraries. This allows for accurate analysis of circuits under the actual effect of aging-induced degradation. We make use of machine learning techniques to overcome infeasible simulation times for individual transistor aging while sustaining high accuracy. In our evaluation on the PULP microprocessor, we achieve predictions of workload-dependent aging-aware standard cells with an average accuracy (R2 score) of 94.7 %. Using the predicted cell libraries in Static Timing Analysis, timing guardbands are reported with an error of less than 0.1 %. We demonstrate that timing guardband requirements can be reduced by up to 21 % by considering specific workloads over worst-case analysis as performed in state-of-the-art tool flows.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks* 一种基于bist的针对移除和oracle引导攻击的弹性动态混淆方案*

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00025

Jonti Talukdar, Siyuan Chen, Amitabh Das, Sohrab Aftabjahani, Peilin Song, K. Chakrabarty

引用次数: 2

Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies 自适应高压应力方法在FinFET技术上实现汽车质量

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00039

S. Traynor, Chen He, Y. Y. Yu, Ken Klein

引用次数: 1

Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin∗ 基于神经孪生体的人工智能加速器故障临界性分析

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00015

Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Siddarth Madala, A. K. Dubey, K. Chakrabarty

{"title":"Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin∗","authors":"Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Siddarth Madala, A. K. Dubey, K. Chakrabarty","doi":"10.1109/ITC50571.2021.00015","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00015","url":null,"abstract":"Owing to the inherent fault tolerance of deep neural network (DNN) models used for classification, many structural faults in the processing elements (PEs) of a systolic array-based AI accelerator are functionally benign. Brute-force fault simulation for determining fault criticality is computationally expensive due to many potential fault sites in the accelerator array and the dependence of criticality characterization of PEs on the functional input data. Supervised learning techniques can be used to accurately estimate fault criticality but it requires ground truth for model training. The ground-truth collection involves extensive and computationally expensive fault simulations. We present a framework for analyzing fault criticality with a negligible amount of ground-truth data. We incorporate the gate-level structural and functional information of the PEs in their \"neural twins\", referred to as \"PE-Nets\". The PE netlist is translated into a trainable PE-Net, where the standard-cell instances are substituted by their corresponding \"Cell-Nets\" and the wires translate to neural connections. Each Cell-Net is a pre-trained DNN that models the Boolean-logic behavior of the corresponding standard cell. In the PE-Net, every neural connection is associated with a bias that represents a perturbation in the signal propagated by that connection. We utilize a recently proposed misclassification-driven training algorithm to sensitize and identify biases that are critical to the functioning of the accelerator for a given application workload. The proposed framework achieves up to 100% accuracy in fault-criticality classification in 16-bit and 32-bit PEs by using the criticality knowledge of only 2% of the total faults in a PE.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8