2021 IEEE International Test Conference (ITC)最新文献_第2页

ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph ACE- pro:用ACE传播图减少函数误差

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00008

Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, J. Liou, Harry H. Chen

{"title":"ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph","authors":"Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, J. Liou, Harry H. Chen","doi":"10.1109/ITC50571.2021.00008","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00008","url":null,"abstract":"Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"10 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124945559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment 用于自动测试设备的3.5Gsps MIPI C-PHY接收电路

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00040

Seongkwan Lee, Minho Kang, Cheolmin Park, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim

引用次数: 1

A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors 一种快速、低成本的CMOS图像传感器嵌入式测试方案

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00007

J. Lefèvre, P. Debaud, P. Girard, A. Virazel

引用次数: 0

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques 基于机器学习技术的晶圆图网格模式识别

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00043

Peter Yi-Yu Liao, Katherine Shu-Min Li, L. Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou

{"title":"WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques","authors":"Peter Yi-Yu Liao, Katherine Shu-Min Li, L. Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou","doi":"10.1109/ITC50571.2021.00043","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00043","url":null,"abstract":"Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a grid pattern recognition methodology taking into account both partial and hidden grid patterns. Hidden defective dies are dies in the grid contour that pass wafer test. However, such dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the potential defective dies in hidden grid patterns and mark them as faulty. As a result, the reliability of products and test cost can be significantly improved. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. A five-phase method is developed to enhance wafer maps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and also achieve 96.45% by Extremely Randomized Trees for all nine common wafer defect types averagely.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"51 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer 求和节点和假求和节点方法:不需要音频分析仪的精确运算放大器交流特性测试

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00052

Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, A. Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, MinhTri Tran, K. Hatayama, Haruo Kobayashi

{"title":"Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer","authors":"Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, A. Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, MinhTri Tran, K. Hatayama, Haruo Kobayashi","doi":"10.1109/ITC50571.2021.00052","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00052","url":null,"abstract":"This paper demonstrates the harmonic distortion measurement of operational amplifiers by applying our proposed summing node method; we show that it can provide low-cost and high-accuracy testing at the mass production shipping stage. Experiments show that measurement accuracy below -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations, and experiments that the summing node method makes the measurement accuracy robust to the harmonics of the signal source providing the sinusoidal input signal to the operational amplifier under test. In other words, a high precision signal generator is not required. Furthermore, we propose the false summing node method, which does not require direct probing of the summing node, in order to avoid oscillation and instability of the video-band operational amplifier under test. Simulations and experiments verify that it can achieve accurate testing without probing of the summing node and it is robust against the ratio variation of the two resistors in the false summing node testing circuit.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Title Page i 第1页

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/itc50571.2021.00001

引用次数: 0

Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration 背景接收机IQ不平衡校正在现场和生产后的测试和校准

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00054

Muslum Emir Avci, S. Ozev

{"title":"Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration","authors":"Muslum Emir Avci, S. Ozev","doi":"10.1109/ITC50571.2021.00054","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00054","url":null,"abstract":"Due to their simplicity, low power consumption, and high-performance, direct conversion transceivers are used widely in RF-front ends. Direct conversion receivers demodulate the signal to its in-phase (I) and quadrature (Q) parts by multiplying the RF signal with two signals with a 90° phase separation. To achieve best performance, I and Q paths should be matched in terms of gain, phase, and have no DC offset. Any impairment in these parameters would result in reduced performance and higher bit error rate. In this work, we propose a BIST scheme for IQ mismatch compensation with low overhead for direct conversion receivers. We use an envelope detector to detect the combined amplitude of the I and Q signals and we use this information to iteratively correct for the receiver’s IQ imbalance. The only requirement on the power detector is a small linear dynamic range (15dB). The conversion gain of the power detector does not need to be known. The proposed method can be used in the mission mode in the background to calibrate any deviations in performance. After the receiver’s IQ imbalance is corrected, it can be used to measure and compensate for any transmitter IQ imbalance in a loopback mode. Simulations and hardware measurements confirm that the proposed technique can measure the imbalances with high accuracy.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128969076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00049

B. Suparjo, Jugantor Chetia, Ankit Shah

引用次数: 0

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process 基于分层高斯过程的多站点射频集成电路测试的晶圆级变化建模

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00018

Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, M. Inoue

{"title":"Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process","authors":"Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, M. Inoue","doi":"10.1109/ITC50571.2021.00018","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00018","url":null,"abstract":"Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131905661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Security EDA Extension through P1687.1 and 1687 Callbacks 通过P1687.1和1687回调的安全EDA扩展

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00050

M. Portolan, Vincent Reynaud, P. Maistri, R. Leveugle, G. D. Natale

引用次数: 3