Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture

Abstract

Hierarchical integrated scan provides many benefits for testing large custom ASIC designs. Physical implementation at full chip level however becomes very challenging as the number of blocks and the levels of hierarchy increase. Additionally, maintaining timing constraints at multiple levels of hierarchy can be very resource intensive. This paper presents a novel framework to overcome these challenges using full chip scan architectural innovation. Our data shows that framework provides significant improvements in terms of test coverage and design convergence time without any design quality loss, thus generating cost saving and accelerating time-to-market.