2021 IEEE International Test Conference (ITC)最新文献_第5页

Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach 高效系统级测试的智能采样:一种鲁棒的机器学习方法

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00013

Chenwei Liu, Jie Ou

{"title":"Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach","authors":"Chenwei Liu, Jie Ou","doi":"10.1109/ITC50571.2021.00013","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00013","url":null,"abstract":"System level tests (SLTs) are important and expensive procedures to ensure high quality of IC products. In the volume production stage with stable yield, efforts such as random sampling have been made to improve testing efficiency. However random sampling doesn’t fully utilize information gathered before SLT and is not optimal. In this paper we propose both supervised (SVM) and unsupervised (AutoEncoder ) machine learning algorithms to predict or estimate the SLT failure based on earlier stage Final Test (FT) data and use the estimated pseudo probabilities to guide the selection of some chips for system level test. Experiments on a real product dataset, consisting of 158 wafers from 8 lots, each with 3118 FT testing variables reveal robustness of the models to data shift such as lot variations and missing test items. Through the gains chart of the models, we provide a flexible smart sampling strategy and demonstrate its potential of reducing SLT testing cost by 40% with minor impact on Defective Parts Per Million (DPPM). Our cases also show that such robust machine learning based sampling approach is very well suited for engaging adaptive test flow optimization to achieve balanced goals of improving test efficiency, reducing cost and ensuring high product quality at the same time.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130227662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling 基于增强标记的晶圆缺陷模式识别半监督框架

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00029

L. Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chung-Lung Hsu

{"title":"Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling","authors":"L. Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chung-Lung Hsu","doi":"10.1109/ITC50571.2021.00029","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00029","url":null,"abstract":"Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133714998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization 用测试故障聚类和重组改进卷诊断和调试

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00034

Mu-Ting Wu, Cheng-Sian Kuo, C. Li, Chris Nigh, Gaurav Bhargava

引用次数: 0

Exploiting Application Tolerance for Functional Safety 利用应用容忍度实现功能安全

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00056

V. Prasanth, R. Parekhji, B. Amrutur

{"title":"Exploiting Application Tolerance for Functional Safety","authors":"V. Prasanth, R. Parekhji, B. Amrutur","doi":"10.1109/ITC50571.2021.00056","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00056","url":null,"abstract":"As the use of safety critical systems is becoming more prevalent, there is a need to reduce the implementation overhead required to provide safety. The conventional design of such systems does not consider application behaviours, thereby resulting in a pessimistic design where the safety provided is often not required during large periods of the application execution. In this paper, we analyse the different phases of an application during its overall execution life cycle, together with the embedded threads to perform specific operations, and propose a new methodology for protection of the safety critical application threads. We show the benefits of this method and the ability to build lower cost systems which are functionally safe using the flexibility which is embedded inside the application itself. Two new application based protection schemes, based on altering the application execution parameters (e.g. control loop frequency) and redundant execution of selective threads, are proposed. For these experiments, we have used commercial off the shelf components without any hardware functional safety features and implemented safety measures by augmenting the application software. Experiments on Electric Vehicle Traction (EVT) and On-Board Charger (OBC) applications indicate overall MIPS savings between 70% to 95%. These results indicate that a careful design of the application can itself be the first step to protect the integrated circuits which drive them.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systematic Hardware Error Identification and Calibration for Massive Multisite Testing 大规模多站点测试的系统硬件误差识别与校准

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00042

Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, S. Ravi, Degang Chen

引用次数: 6

Study on High-Accuracy and Low-Cost Recycled FPGA Detection 高精度、低成本回收FPGA检测研究

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00021

Foisal Ahmed, Michihiro Shintani, M. Inoue

{"title":"Study on High-Accuracy and Low-Cost Recycled FPGA Detection","authors":"Foisal Ahmed, Michihiro Shintani, M. Inoue","doi":"10.1109/ITC50571.2021.00021","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00021","url":null,"abstract":"This research work presents a novel method for the detection of recycled field-programmable gate arrays (FPGAs). In this method, delay information of all paths in look-up tables (LUTs) of configurable logic blocks in the FPGAs is analyzed exhaustively by employing an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path of all LUTs in the FPGA, it considerably increases the RO measurement cost. Furthermore, X-FP yields a large amount of measurement data causing the \"curse of dimensionality\" problem when used as a feature vector in the machine learning (ML) based detection system. To combat these challenges while applying the X-FP characterization, we additionally propose two techniques for realizing accurate and efficient recycled FPGA detection: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement. The WID modeling properly reflects the process variation of each FPGA, and model parameters extracted by the modeling are utilized as a feature vector in the ML-based detection to classify target FPGAs as either fresh or aged. Through experiments using commercial FPGAs, we demonstrate that the proposed method combining the VP and WID modeling on the X-FP characterization achieves high-accuracy recycled FPGA detection at a low measurement cost.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131138282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis 您的安全测试基础设施是否足够安全?:基于使用瞬态行为分析的延迟测试模式的攻击

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00048

Sergej Meschkov, Dennis R. E. Gnad, Jonas Krautter, M. Tahoori

引用次数: 1

Characterizing Corruptibility of Logic Locks using ATPG 用ATPG表征逻辑锁的可损坏性

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00030

Danielle Duvalsaint, R. D. Blanton

引用次数: 0

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment 在不可信环境中使用代客密钥进行逻辑锁定感知测试

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00026

M. S. Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, M. Tehranipoor

{"title":"LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment","authors":"M. S. Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, M. Tehranipoor","doi":"10.1109/ITC50571.2021.00026","DOIUrl":"https://doi.org/10.1109/ITC50571.2021.00026","url":null,"abstract":"The ever-increasing cost and complexity of cutting-edge manufacturing and test processes have migrated the semiconductor industry towards a globalized business model. With many untrusted entities involved in the supply chain located across the globe, original intellectual property (IP) owners face threats such as IP theft/piracy, tampering, counterfeiting, reverse engineering, and overproduction. Logic locking has emerged as a promising solution to protect integrated circuits (ICs) against supply chain vulnerabilities. It inserts key gates to corrupt circuit functionality for incorrect key inputs. A logic-locked chip test can be performed either before or after chip activation (becoming unlocked) by loading the unlocking key into the on-chip tamperproof memory. However, both pre-activation and post-activation tests suffer from lower test coverage, higher test cost, and critical security vulnerabilities. To address the shortcomings, we propose LL-ATPG, a logic-locking aware test method that applies a set of valet (dummy) keys based on a target test coverage to perform manufacturing test in an untrusted environment. LL-ATPG achieves high test coverage and minimizes test time overhead when testing the logic-locked chip before activation without sharing the unlocking key. We perform security analysis of LL-ATPG and experimentally demonstrate that sharing the valet keys with the untrusted foundry does not create additional vulnerability for the underlying locking method.","PeriodicalId":147006,"journal":{"name":"2021 IEEE International Test Conference (ITC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning 利用累积学习预测生产试验中的最小工作电压

2021 IEEE International Test Conference (ITC) Pub Date : 2021-10-01 DOI: 10.1109/ITC50571.2021.00012

Yen-Ting Kuo, Wei-Chen Lin, C. Chen, Chao-Ho Hsieh, Chien-Mo James Li, Eric Jia-Wei Fang, S. Hsueh

引用次数: 2