Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis

The existing work on securing test infrastructure is based on the assumption of restricting or encrypting access to the sensitive information, which otherwise can be accessed by the scan chains or similar test access ports. Hence, the (publicly) accessible outputs or test infrastructure subset supposedly do not leak secret information. Since the on-chip test infrastructure is reused in-field for achieving functional safety requirements, disabling them completely after manufacturing test phase is not an option. In this work we invalidate this assumption by showing that having access to (small delay) test results on insensitive (public) outputs can in fact reveal secret data. Using real hardware, we have performed template attacks using the results of delay testing on the output of cryptographic circuits and were able to retrieve the key with very few test inputs. This template attack requires only few random patterns on the victim device, which could be different from the device used for template building.