Study on High-Accuracy and Low-Cost Recycled FPGA Detection

Abstract

This research work presents a novel method for the detection of recycled field-programmable gate arrays (FPGAs). In this method, delay information of all paths in look-up tables (LUTs) of configurable logic blocks in the FPGAs is analyzed exhaustively by employing an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path of all LUTs in the FPGA, it considerably increases the RO measurement cost. Furthermore, X-FP yields a large amount of measurement data causing the "curse of dimensionality" problem when used as a feature vector in the machine learning (ML) based detection system. To combat these challenges while applying the X-FP characterization, we additionally propose two techniques for realizing accurate and efficient recycled FPGA detection: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement. The WID modeling properly reflects the process variation of each FPGA, and model parameters extracted by the modeling are utilized as a feature vector in the ML-based detection to classify target FPGAs as either fresh or aged. Through experiments using commercial FPGAs, we demonstrate that the proposed method combining the VP and WID modeling on the X-FP characterization achieves high-accuracy recycled FPGA detection at a low measurement cost.