Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory

Abstract

Computation in Memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.