2008 2nd Electronics System-Integration Technology Conference最新文献

{"title":"Evaluation of printing parameters and substrate treatmet over the quality of printed silver traces","authors":"R. Bonadiman, Marco E. Marques, G. Freitas, T. Reinikainen","doi":"10.1109/ESTC.2008.4684550","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684550","url":null,"abstract":"Printed electronics provide a promising potential pathway towards the design of low cost products. Manufacturing electronic devices by printing techniques using nano-size material particles at low temperatures can revolutionize the electronics industry in coming years. Products based on printable electronics might include ultra cheap radio-frequency identification tags (RFID), inexpensive and disposable displays/electronic paper, interior connections, parts of electronic assemblies (e.g. PWB and phone chassis), sensors, memories, and wearable user interfaces. Moreover, PWBs could be replaced by an inkjet printed substrate. Direct printing of nanoparticle inks could also be used for the electrical interconnection of components (traces). Considering this scenario, the challenge is to provide sufficient quality of interconnecting traces considering the selection of appropriate material, more precise material deposition process and sintering. Adequate process control would lead to suitable electrical conductivity of printed interconnections.In this work the influence of the printing parameters - such as ink temperature, cartridge ink height and the plate temperature (surface over which the substrate that receives the ink is fixed) - in the print quality were evaluated. These parameters are very important in order to obtain conductive traces with good resolution and reproducibility. Another important factor is the treatment of the substrate. It also defines the quality and resolution of the traces since the chemical interaction between the ink and the surface (defined by the surface energy) determine how the ink will spread over the substrate. An optimized surface can be obtained by seeking the best relation between the metal trace adhesion and trace resolution. The surface treatment can be made in different ways aiming at an optimal value for the surface energy. Common surfaces treatments are plasma, corona treatment, and chemical treatment. In this work, polyimide substrates were submitted to surface treatment using corona and a chemical solution. The surface energy was evaluated and an optimum surface energy value was determined.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"“glassPack” — photonic packaging using thin glass foils for electrical-optical circuit boards (EOCB) and sensor modules","authors":"H. Schroder, Norbert Arndt-Staufenbiel, L. Brusberg","doi":"10.1109/ESTC.2008.4684532","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684532","url":null,"abstract":"The ldquoglassPackrdquo-concept will be introduced as a new packaging technologies platform for a wide area of opto-electronic applications like optical backplane, electrical-optical circuit boards (EOCB) and sensors. The usage of thin glass foils of some tens of microns thickness as substrate and interconnection material is the crucial point of the concept. First realizations will be presented.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127647425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating design, manufacture and test using capability measures","authors":"J. M. Gilbert","doi":"10.1109/ESTC.2008.4684479","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684479","url":null,"abstract":"Successful electronic products rely on a combination of good design, appropriate manufacturing processes and effective test and inspection. In order to achieve all of these within a highly cost constrained environment requires that sufficient, but not excessive, resources are applied to each area. One problem which makes it difficult to balance the allocation of resources is that different measures of performance are used in each context. In the design domain, the objectives are typically design centring, robust design, part count reduction or component cost reduction. Objectives in manufacturing processes are typically yield maximisation, process capability, defect reduction etc. In the test arena, the aim is typically to maximise test coverage and minimising test/inspection times. Given this plethora of different measures of performance, it is difficult to assess trade-offs between different domains and decide appropriate resource allocations.In order to address this problem we have proposed a unified measure of capability across the design/manufacture/test spectrum. This is based on the process capability measure Cpk which has been adapted to measure functional capability: the ability of a design to meet its performance specification in the presence of component parameter variations, and to test capability: the ability of test/inspection processes to correctly identify defects without erroneously indicating defects which are not present. These capability measures may be related to the costs arising from defects through scrap, rework and warranty returns through a failure modes and effects analysis (FMEA) and a quality cost mapping process. This makes it possible to quantify and compare the cost consequences of design decisions. This unifying analysis methodology is termed electronic conformability analysis (eCA). The paper introduces the eCA methodology, explains the functional, manufacture and test capability measures and shows how these may be related to quality cost. The application of the methodology to a simple example circuit is presented.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116041053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip chip interconnects qualified for advanced low-k chips with SnCu bumps by alloying Cu/Sn plated stack","authors":"H. Ezawa, M. Uchida, M. Miura, T. Togasaki, T. Iijima, T. Migita, K. Higuhci","doi":"10.1109/ESTC.2008.4684439","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684439","url":null,"abstract":"There are few reports of SnCu bumping by electroplating targeting on process qualification for an advanced low-k chips. In this study, the creep behavior of the SnCu solder alloy, fabricated by alloying a layered Cu/Sn plated stack, has been investigated in the actual feature size of flip chip interconnects in packages. The advantage of the SnCu bumps showing higher creep rates has led to reduction of chip package interaction. No reliability issues of the SnCu bumping with a pitch of 150 mum have been also confirmed for the 65 nm advanced low-k chips in flip chip interconnects. Integrity of the SnCu interconnects after thermal cycling has been discussed by the grain structures of the SnCu alloys.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"18 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Carbon nanotube (CNT) filled adhesives for microelectronic packaging","authors":"M. Wirts-Rutters, M. Heimann, J. Kolbe, K. Wolter","doi":"10.1109/ESTC.2008.4684498","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684498","url":null,"abstract":"This project evaluated the use of carbon nanotubes as a filler in electrically conducting adhesives in order to enhance the electrical, mechanical and thermal performance. As the carbon nanotubes caused a marked increase in the viscosity of the adhesive, a low viscosity polymer matrix (< 100 mPas) was chosen. This allowed a high CNT content. Multi-wall carbon nanotubes (MWNTs) were chosen for the experiments because these are available in favorable quantities and at reasonable prices. In order to enhance the dispersion properties, the MWNTs were also treated chemically via ozone/UV and low pressure plasma. For mixing the MWNTs into the polymer matrix different methodologies were tested. Ultrasound was found to be a very effective method, but the dispersion energy drops dramatically when viscosities above 10,000 mPas are reached. Hence high viscosity adhesives were treated using a calander as described in [1]. In general, good dispersion could be achieved by applying combinations of these two dispersion techniques. Adhesives were produced with varying CNT content, different CNT types and using different dispersion techniques. The influence of these parameters on the electrical resistance, thermal conductivity, impedance behavior and mechanical strength was investigated. In parallel, many samples were analyzed by TEM in order to get detailed knowledge of the adhesive nanostructure and learn how this structure is influenced by the above- mentioned parameters. Furthermore, the absorption of microwave radiation by the samples was investigated in order to further our understanding of microwave absorption by CNT-filled composites. Based on these results, the two standard formulations showing the best performance were chosen for bonding SMD components on a test assembly. For the curing of the adhesives two methods were used: Curing by microwave radiation and curing in a conventional oven at 130degC. Whilst the conventional curing took 30 minutes, it was possible to completely cure the adhesives using microwave radiation in only 3 minutes. Finally, the bonded assemblies were subjected to a system integrity test. The mechanical stability of the adhesive bonds showed very high resistance to ageing after exposure to humidity and after 1000 thermal cycles.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"126 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120987227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"X-ray nanoCT of electronic components: Visualizing of internal 3D-structures with submicrometer resolution","authors":"A. Egbert","doi":"10.1109/ESTC.2008.4684562","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684562","url":null,"abstract":"High-resolution X-ray computed tomography (CT) allows the visualisation and failure analysis of the internal microstructure of small electronic devices - even if they have complicated 3D-structures where 2D X-ray microscopy would give unclear information. During the last decade, CT has progressed to higher resolution and faster reconstruction of the 3D-volume. Most recently it even allows a three-dimensional look into the inside of materials with submicron resolution. By means of nanofocusreg tube technology, nanoCTreg-systems are pushing forward into application fields that were exclusive to expensive synchrotron techniques. The new nanotomreg of phoenix|X-ray is a very compact laboratory system specialised for the analysis of small samples with the exceptional submicron voxel-resolution down to 500 nm (0.5 microns). It is the first 180 kV nanofocusreg computed tomography system in the world which is tailored specifically to the highest-resolution applications in the fields of electronics, micro mechanics or materials science. Therefore it is particularly suitable for nanoCTreg-examination of electronic packages, sensors, actuators, complex micro electronic components with concealing parts such as capacitors or stacked dies and material samples of every type like synthetic materials, ceramics or composites. Any internal difference in material, density or porosity within a sample can be visualised and data like distances or pore volumes can be measured. By granting the user the ability to navigate the internal structure of an object slice-by-slice in a nondestructive manner, the nanotomreg creates new possibilities for sample analysis per mouse click which have thus far been unreachable. NanoCTreg widely expands the spectrum of detectable micro-structures and is ideal for the non-destructive inspection of compact but complex micro mechanic parts or electronic devices. The nanotomreg opens a new dimension of 3D-microanalysis and will partially replace destructive methods - saving costs and time per sample inspected.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121286765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanical characterisation of thin metal layers by modelling of the nanoindentation experiment","authors":"O. Wittler, R. Mrossko, E. Kaulfersch, B. Wunderle, B. Michel","doi":"10.1109/ESTC.2008.4684488","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684488","url":null,"abstract":"Obtaining material data for thin metal layers is a mayor issue in the reliability assessment of microelectronic products. Therefore a method for obtaining elastic-plastic material data is analyzed and discussed in this paper. It is based on the nanoindentation of a film on a silicon substrate and the modeling of it. Thus it becomes possible to fit specific material models to the indentation experiment. Results are shown for two AlSiCu layers.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121325748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The challenge of commercialized crystalline silicon solar cell","authors":"M. Wei, S. Chang, C.M. Lee, R. Chuang","doi":"10.1109/ESTC.2008.4684319","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684319","url":null,"abstract":"As one of the most rapidly growing industry in recent years, commercialized crystalline silicon solar cell has faced a lot of challenge, especially from its similar application, the thin film solar cell technology. In order to survive at this crucial competition, there are several ways to overcome the difficulties. However, all the evidence point to the same way only, that is to apply the high efficiency technologies on commercialized process.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126682383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Condition indicators for reliability monitoring of microsystems","authors":"T. Eckert, O. Bochow-Neß, A. Middendorf, K. Tetzner, H. Reichl","doi":"10.1109/ESTC.2008.4684494","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684494","url":null,"abstract":"Information about the condition of electronic systems in use supports reliability, maintenance and safety. This paper describes an approach to condition monitoring using monitoring structures. With such structures, the remaining life time of a system can be estimated in field use under varying load. The design and evaluation of monitor structures sensible to thermo-mechanical load is shown. Technological boundaries are taken into consideration and an example of a flip chip based monitor structure is presented. The tailoring of the structure regarding the failure model is described in general and in detail. To achieve a robust structure, parametric finite element modeling of technological fabrication tolerance is carried out to determine the selectivity of the structures. Analyzing the results of the finite element study, conclusions concerning the statistical distribution of the failure are drawn and suggestions are made to improve the accuracy of condition monitoring.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121511780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thick film modules assembled to flexible printed circuits","authors":"M. Detert, L. Rebenklau, S. Schroder, K. Wolter","doi":"10.1109/ESTC.2008.4684467","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684467","url":null,"abstract":"The creation of a basic concept for the safe connection of various technologies of electronic packaging to a great final overall structure mix will be more important in the next years. Due to the increasing demands, it is clear, that all incumbent solutions of the packaging will use the advantageous properties for a total hybrid concept. To ensure the reliability of such a solution, we have to guarantee a reliable interface between the various technology concepts with the practical constructions. Consideration of existing standards and tools of quality management is to integrate. The landscape and process necessary for evaluation methods are fully present and potential problem areas are the basis of practical studies show. The task is an example of the area array connection between the flexible printed circuits and the assembled thick film modules in different geometrical dimensions. So we used different geometries in the pitch and different joining technologies in the manufactured thick film modules. We made some investigations with our manufactures thick film modules, which we assembled on polyimide substrates. During the characterization during accelerated test methods we obtained a lot of interesting data about this technology combination. We describe our methods for manufacturing of samples, the test methods and our final view to the results. The use of flexible flat cables (FFC) and flexible printed circuits (FPC) constantly increases in the next years. The development of competitive products can be improved on basis of these technologies. The advantages within the range reliability and costs could be used however only with the consideration of a complete view of the entire process chain efficiently and trend-setting.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}