Flip chip interconnects qualified for advanced low-k chips with SnCu bumps by alloying Cu/Sn plated stack

Abstract

There are few reports of SnCu bumping by electroplating targeting on process qualification for an advanced low-k chips. In this study, the creep behavior of the SnCu solder alloy, fabricated by alloying a layered Cu/Sn plated stack, has been investigated in the actual feature size of flip chip interconnects in packages. The advantage of the SnCu bumps showing higher creep rates has led to reduction of chip package interaction. No reliability issues of the SnCu bumping with a pitch of 150 mum have been also confirmed for the 65 nm advanced low-k chips in flip chip interconnects. Integrity of the SnCu interconnects after thermal cycling has been discussed by the grain structures of the SnCu alloys.