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2008 2nd Electronics System-Integration Technology Conference最新文献

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TSV process using bottom-up Cu electroplating and its reliability test TSV工艺采用自下而上镀铜及其可靠性试验
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684427
H. Chang, Y. Shih, C. Hsu, Z. Hsiao, C. Chiang, Y.H. Chen, K. Chiang
{"title":"TSV process using bottom-up Cu electroplating and its reliability test","authors":"H. Chang, Y. Shih, C. Hsu, Z. Hsiao, C. Chiang, Y.H. Chen, K. Chiang","doi":"10.1109/ESTC.2008.4684427","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684427","url":null,"abstract":"TSV (through silicon via) is a core technology in 3D IC package. The micro vias can be made by etching or laser drilling. Standard processes for TSV filling begin with seed layer deposition, followed by blind vias copper electroplating. If the aspect ratio of the TSV is higher than 5:1, the costly MOCVD process needs to be used to deposit the seed layer with good step coverage. A special designed electroplating machine and solution for high aspect ratio copper electroplating is needed. Some researchers even use PRP (periodic reverse plating) for void free copper electroplating instead of traditional DC power supply.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124271939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Reliability of lead free solder SAC 305 for chip components depending on various factors 芯片元件的无铅焊料SAC 305的可靠性取决于各种因素
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684393
O. Russkikh, J. Šandera
{"title":"Reliability of lead free solder SAC 305 for chip components depending on various factors","authors":"O. Russkikh, J. Šandera","doi":"10.1109/ESTC.2008.4684393","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684393","url":null,"abstract":"The paper gives results of practical tests concerning reliability of solder joints forged with the lead free solder SAC305. Various finishing, bending pads and methods of soldering were tested.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and performance of metal conductors for stretchable electronic circuits 可伸缩电子电路用金属导体的设计和性能
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1108/03056120910928699
Mario Gonzalez, F. Axisa, F. Bossuyt, Yung-Yu Hsu, Bart Vandevelde, J. Vanfleteren
{"title":"Design and performance of metal conductors for stretchable electronic circuits","authors":"Mario Gonzalez, F. Axisa, F. Bossuyt, Yung-Yu Hsu, Bart Vandevelde, J. Vanfleteren","doi":"10.1108/03056120910928699","DOIUrl":"https://doi.org/10.1108/03056120910928699","url":null,"abstract":"In this paper we review the mechanical properties and reliability results of stretchable interconnections used for electronic applications. These interconnections were produced by a Moulded Interconnect Device (MID) technology in which a specially designed metal interconnection if fully embedded with an elastic material such as polyurethane or silicone. In order to get a first impression of the expected damage in the interconnections, this research employs Finite Element Modelling (FEM) to analyse the physical behaviour of stretchable interconnects under different loading conditions. Moreover, the fatigue life of a copper interconnect embedded into a silicone matrix has been evaluated using the Coffin-Manson relation and FEM.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127330668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Stacking of ultra-thin film packages 超薄薄膜包装的堆叠
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684337
C. Ko, Y. Shih, Jing-Yao Chang, T. Kuo, Yu-Hua Chen, A. Ostmann, D. Manessis
{"title":"Stacking of ultra-thin film packages","authors":"C. Ko, Y. Shih, Jing-Yao Chang, T. Kuo, Yu-Hua Chen, A. Ostmann, D. Manessis","doi":"10.1109/ESTC.2008.4684337","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684337","url":null,"abstract":"This paper brings into light a new ultra-thin and highly flexible package with embedded active chips. In this technology, no supporting and permanent substrates were needed. Copper foil was used as temporal substrate, and it became the bottom circuit after patterning and etching processes. Ultra-thin chips with 20~25 mum thickness were assembled directly on the structured copper foils in a flip-chip fashion. The gap between chip and copper foil was only about 10 mum. Subsequently, the chips were embedded into flexible adhesive/polyimide polymer layers or alternatively in highly elastic polyurethane materials, with a copper foil always laminated on the top. The resultant ultra-thin film package (UTFP) has a thickness of 100 mum only. Each package sticking on a rod with 10 mm diameter could pass the electrical measuring. Stacking of three-layer chip embedded packages had also been realized and passed electrical measurements. The process details on each core technique will be disclosed, and some results will be presented in the paper.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Biocompatible DC-microelectrode array 生物相容性直流微电极阵列
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684388
J. Derix, G. Gerlach, S. Perike, S. Wetzel, R. Funk
{"title":"Biocompatible DC-microelectrode array","authors":"J. Derix, G. Gerlach, S. Perike, S. Wetzel, R. Funk","doi":"10.1109/ESTC.2008.4684388","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684388","url":null,"abstract":"A new kind of microelectrode array is presented that uses an arrangement of microfluidic channels filled with an electrolyte solution as electrodes. This allows for the spatially resolved, long term application of direct currents to cells in a culture medium on the chip. A crucial task in the production of the chip is the integration of a nanoporous polymer membrane that acts as a basis for cell adhesion and as a support for the layer that contains the microelectrode openings.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Innovative Optical and Electronic Interconnect Printed Circuit Board Manufacturing research 创新光学与电子互连印刷电路板制造研究
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684466
David R. Selviah, D. Hutt, A. Walker, K. Wang, F. Fernández, P. Conway, D. Milward, I. Papakonstantinou, H. Baghsiahi, J. Chappell, S. S. Zakariyah, A. Mccarthy, H. Suyal
{"title":"Innovative Optical and Electronic Interconnect Printed Circuit Board Manufacturing research","authors":"David R. Selviah, D. Hutt, A. Walker, K. Wang, F. Fernández, P. Conway, D. Milward, I. Papakonstantinou, H. Baghsiahi, J. Chappell, S. S. Zakariyah, A. Mccarthy, H. Suyal","doi":"10.1109/ESTC.2008.4684466","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684466","url":null,"abstract":"An overview of the pound1.3 million EPSRC and company matched funded Innovative electronics Manufacturing Research Centre (IeMRC) Flagship project between 3 UK universities and 10 companies entitled ldquointegrated optical and electronic interconnect PCB manufacturingrdquo. The project aims to develop of optical waveguide design rules, layout software, fabrication methods compatible with commercial production, characterisation techniques and optical connector design to provide a supply chain for Polymer Multimode Optical Waveguide Printed Circuit Boards (OPCB) for 10 Gb/s board-to-board interconnections.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126732391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Modeling and analysis of return-current paths for microstrip-to-microstrip via transitions 微带间转换回流路径的建模与分析
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684546
I. Ndip, F. Ohnimus, S. Guttowski, H. Reichl
{"title":"Modeling and analysis of return-current paths for microstrip-to-microstrip via transitions","authors":"I. Ndip, F. Ohnimus, S. Guttowski, H. Reichl","doi":"10.1109/ESTC.2008.4684546","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684546","url":null,"abstract":"In this contribution, the return-current paths for single-ended microstrip-to-microstrip via transitions in conventional layer stack-ups are modeled and analyzed. Electromagnetic reliability (EMR) problems which occur in these layer stack-ups, because the return-currents are not properly managed are discussed. Finally, a layer stack-up with well defined return-current paths, which overcomes the limitations of traditional layer stack-ups, is proposed.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114908589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel optical transmitter and receiver for parallel optical interconnects on PCB-level 基于pcb级并行光互连的新型光收发器
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684420
K. Nieweglowski, K. Wolter
{"title":"Novel optical transmitter and receiver for parallel optical interconnects on PCB-level","authors":"K. Nieweglowski, K. Wolter","doi":"10.1109/ESTC.2008.4684420","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684420","url":null,"abstract":"In this contribution a concept of ceramic transmitter and receiver module for assembly on electro-optical printed circuit board with parallel optical interconnects is presented. The realized pitch of parallel optical interconnection amounts to 250 mum. The solution for realization of the indirect optical coupling basing on micro-optical coupling element will be shown. Described optical analysis in regard to the optical coupling between link components (VCSEL, micro-optical coupling elements and p-i-n-photodiode array) will define the conditions for alignment process of optoelectronic devices and micro-optics. The design and realization of an optical multi-chip module basing on ceramic interposer will be presented in detail. An approach for the flux free solder-bumped flip chip assembly process of optoelectronic components will be shown. Finally the first demonstrator of the optical transmitter and receiver module will be demonstrated.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117035936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Bended interconnection using Graded Index optical waveguide for high speed optical communication 高速光通信用渐变折射率光波导弯曲互连
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684482
K. Yasuda, K. Ota, M. Matsushima, K. Fujimoto
{"title":"Bended interconnection using Graded Index optical waveguide for high speed optical communication","authors":"K. Yasuda, K. Ota, M. Matsushima, K. Fujimoto","doi":"10.1109/ESTC.2008.4684482","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684482","url":null,"abstract":"The interchip information transmission by the optical signal is promising in the band of 10 GHz or more in the future. Since high speed transmissions are more possible than alignment easiness and the multimode waveguides by making of the core diameter a large diameter, we proposes the use of the GI (Graded-Index) waveguide that has the curved structure without the reflection mirror. In this study, it was clarified that the power loss was small regardless of a small curvature. A periodic loss related to the length of the straight line part of the waveguide was found in the analysis by using the ray tracing method. The correction curve and the elliptic curve were proposed as the solution of the problem.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129879273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nano Evaluation in Electronics Packaging 电子封装中的纳米评价
2008 2nd Electronics System-Integration Technology Conference Pub Date : 2008-11-21 DOI: 10.1109/ESTC.2008.4684493
M. Oppermann, H. Heuer, N. Meyendorf, K. Wolter
{"title":"Nano Evaluation in Electronics Packaging","authors":"M. Oppermann, H. Heuer, N. Meyendorf, K. Wolter","doi":"10.1109/ESTC.2008.4684493","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684493","url":null,"abstract":"The challenge of nano packaging requires new non-destructive evaluation (NDE) techniques to detect and characterize very small defects like transportation phenomenon, Kirkendall voids or micro cracks. Imaging technologies with resolutions in the submicron range are the desire. Possible evaluation methods are for example x-ray microscopy, x-ray tomography, ultrasonic microscopy and thermal microscopy. However, techniques with this resolution can not be found on the market. The ldquocenter for non-destructive nano evaluation of electronic packagingrdquo (nanoevareg) is taken up to develop this equipment in cooperation with the electronics industry and to transfer the knowledge to colleagues in industries and research institutions. The new center is a common organization of Fraunhofer IZFP-D and the electronics packaging lab with its centre of microtechnical manufacturing (ZmuP) of the Technische Universitat Dresden.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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