2008 2nd Electronics System-Integration Technology Conference最新文献

{"title":"Mechanical fatigue properties of heavy aluminium wire bonds for power applications","authors":"Lutz Merkle, T. Kaden, Marcus Sonner, A. Gademann, J. Turki, C. Dresbach, Matthias Petzold","doi":"10.1109/ESTC.2008.4684554","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684554","url":null,"abstract":"In this study, a technology-oriented simplified mechanical fatigue testing approach for aluminium heavy wire bonds as well as first experimental results are presented. In the test setup, bonding wires were displacement-controlled loaded with different amplitudes at room temperature and the corresponding cycles to failure were experimentally determined. Loop geometries were varied in a technological meaningful range. The experimentally determined endurance curves show a strong influence of the bonding geometry on the lifetime of the bonding wires. In addition to testing, a three dimensional finite element model of the different bonding wire geometries was developed in order to quantify the local deformation situation at the failure site in terms of equivalent strain. The global mechanical properties used for the simulations were determined by tensile tests of unprocessed bonding wires. The experimental results in terms of number of cycles to failure could be represented as a function of the change in equivalent strain at the heel for the different bond loop geometries. Using a common double-logarithmic endurance plot, the results for the different bond loop geometries could be approximated by a linear dependency. This result is in accordance with the expectation that a Coffin-Manson approach can be applied to predict the life time of the aluminium wire bonds. From these results, it can be concluded that the experimental testing approach and the applied simulation model is applicable to understand the effect of different bonding loop geometries on the number of cycle to failure. For a more generalized understanding, it has to be taken into consideration that the mechanical properties close to the heel were affected by the bonding process prior to fatigue loading. In form of a preliminary study, it is shown that spherical indentation testing on cross sections of the bonded wires provides a useful methodical approach to characterize these variations and to extract the local material properties for further expanded modelling.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127403428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of geometrical parameters of mutual parallel paths on process of disturbances propagation","authors":"W. Kalita, W. Sabat, D. Klepacki, K. Kamuda","doi":"10.1109/ESTC.2008.4684503","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684503","url":null,"abstract":"The problems connected with electromagnetic couplings between mutual parallel paths in planar structures made in thick-film technology have been presented in the paper. The influence of geometrical configuration of thick-film path systems on shape of transfer function between them has been analyzed. The modification of transfer function under changes of the particular geometrical factors has been quantitatively determined using elaborated computer programs. The results of calculations have been presented for the selected path configurations.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip chip based packaging solution for high current driver chips used in automotive applications","authors":"B. Vandevelde, B. Vandecasteele, D. Vanderstraeten, G. Brizar, E. Blansaer","doi":"10.1109/ESTC.2008.4684415","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684415","url":null,"abstract":"In this work, flip chip is investigated as an alternative assembly technology for packaging applications requiring driving high electrical currents up to 10A and high IC power dissipation. Currently, automotive applications with components driving (temporary) high electric currents are mainly using wire bond based packaging solutions because of cost reason. However, wire bonds with standard diameters are limited in their capability of driving large currents due to the joule heating, which results in unacceptable high temperatures as shown in this paper by analytical calculations, non linear finite element model simulations and experiments on test packages. The temperature increase exponentially grows with current due to the joule heating effect. The flip chip assembly with lead-free solder interconnects, thick top metallization on the die and adapted PCB has proven to be capable to drive currents up to 10A without substantial temperature increase.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117288257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation mechanism of Ag-epoxy conductive adhesive joints by heat and humidity exposure","authors":"Sun Sik Kim, Keun-Soo Kim, K. Suganuma, H. Tanaka","doi":"10.1109/ESTC.2008.4684472","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684472","url":null,"abstract":"Isotropic conductive adhesives (ICA), such as Ag-epoxy pastes, have been recognized as one of the ecological alternatives to lead-bearing solders in surface mount technology (SMT) applications. Although Ag-epoxy conductive adhesives possess many advantages as an alternative, they still have several drawbacks to be clarified. The present study shows the degradation mechanism of mounted chip components with Ag-epoxy conductive adhesives under two different environmental tests: the thermal cycle between -40 and 125degC and the humid exposure of 85degC/85%RH. The electrical resistance of the chip component circuits during both environmental tests increased with exposure time. Under the thermal cycles, micro-cracks were accumulated at the Sn/epoxy resin interface. In addition, there were no secondary phases such as oxides at the interface. On the other hand, under the humid atmosphere, thin Sn-oxide layers were formed inhomogeneously on the surface of Sn plating joined with Ag-epoxy conductive adhesives. The formation of additional defects at the joint interface, such as micro-cracks and Sn-oxide layers, causes the interfacial degradation of the mounted chip components. The detailed degradation mechanisms of the Ag-epoxy conductive adhesive joints are to be discussed.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123597788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CO2 detector based on organo-siloxane supramolecular polymer","authors":"G. Ţelipan, L. Pîslaru-Dănescu, C. Racles","doi":"10.1109/ESTC.2008.4684529","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684529","url":null,"abstract":"The sensor was made by thick and thin film technology. An alumina substrate 6times6times0.5 mm was used. On the substrate was screen-printed an interdigitated electrode array by Au conductive ink. The sensitive layer the organo-siloxane supramolecular polymers was dissolved in chloroform and was deposed by spin coating on the substrate over electrode in the 200 nm thickness. The sensor was tested in 100 and 1000 ppm concentration CO2 and for 30 minutes gas exposure were obtained the voltage values of 92 mV and 970 mV for 100 ppm and 1000 ppm CO2. The detector is composed by the sensor and electronic device of signal conditioning.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129479930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MicroLens/UV-LED array packaging for dynamic and static alignment","authors":"M. Luetzelschwab, M. Desmulliez, D. Weiland","doi":"10.1109/ESTC.2008.4684509","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684509","url":null,"abstract":"This paper presents a fully integrated packaging solution that permits the static and active alignment of a microLens array placed on top of a micro-UV-LED array. The entire process is manufactured by UV-lithography using predominantly the photoresists SU8 and THB. The processing temperature for all steps is below 120degC.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New developments for highest integration density in Polymer Thick-film Technology","authors":"M. Luniak, K. Wolter","doi":"10.1109/ESTC.2008.4684449","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684449","url":null,"abstract":"The development of innovative electronic devices is characterized by increasing demands with respect to functionality, further miniaturization, high reliability and simultaneously lower manufacturing costs. The study of Polymer Thick-film Technology (PTF) regarding improvements in print resolution and conductivity demonstrates its potential for an application in microelectronics. Polymeric thick-film technology is implemented in the production of electronic circuits since the 50psilas. It was primarily used in the production of cost saving hybrid circuits. However the used materials in the past did not match the now common specifications regarding thermal properties and migration behaviour. Now the requirements regarding resolution, material cleanness and reliability are unlikely higher. Therefore different materials and processes of this technology are described. Particularly the screen-printing of polymer pastes filled with silver particles is characterized. While the minimal line width of thick-film circuits was 120...200 mum 10 years ago, one now is capable to reduce line width to fewer than 100 mum. But line widths with a pitch fewer than 120 mum are necessary for a wafer level package because of always increasing requirements regarding the number of chip connections. Today we already find thick-film circuits with line resolutions smaller than 30 mum. With an additional process step not only the conductivity but also the reliability of such printed structures can be improved. Surface topography, shear strength and electrical parameters (square resistance, impedance and current carrying capacity) were determined using various methods. The conducted studies in fine-line screen-printing of polymer pastes could demonstrate that the normally used thin-film technology for wafer level redistribution can be replaced in low-cost applications.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130869367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of wire electrolytic-spark hybrid machining of silicon solar wafer and surface characteristics","authors":"W. Wang, Z.D. Liu, Z. Tian, Y. Huang, Z.X. Liu, N.N. Ekere","doi":"10.1109/ESTC.2008.4684417","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684417","url":null,"abstract":"In this paper, a new slicing method based on wire WESHM strategy, which combines electric discharge and anodic etching into a whole process, is presented. Experiments were conducted to evaluate effect of the machining rate, surface quality and wafer thickness of low resistance (0.1~10Omegamiddotcm) mono-crystalline and poly-crystalline silicon on the wafer surface characteristics. The results show that with optimal electrical parameters and electrolyte, the maxim machining rate is ~ 600 mm2/min and wafer thickness is less than 120 mum. In comparison to wire electrical discharge machining (WEDM), heat affected zone and harmful metal residual are remarkably diminished. Dense micron and submicron conic pores, which may be introduced by high temperature electrolytic erosion, are located in the craters and surface texture is quite even giving a dark color. The reflectance of light on the samples was measured to evaluate the effect of this texturing method. Experimental results show the reflectance on sliced wafer is even lower than the standard solar cells. Furthermore, in the case of cone-shaped pores for the formed surface, a fractal analysis was investigated to describe the extremely complicated surface structure, which was related to the reflectivity and could be useful to characterize surface topography properly. It is demonstrated that the wire electrolytic-spark hybrid machining (WESHM) technique has good potential for achieving high quality silicon wafer slices, and can provide a high efficiency, low-cost technique for the production of the low resistance silicon used in the photovoltaic industry.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"1992 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal impact of randomly distributed solder voids on Rth-JC of MOSFETs","authors":"Liu Chen, M. Paulasto-Krockel, U. Frohler, D. Schweitzer, H. Pape","doi":"10.1109/ESTC.2008.4684356","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684356","url":null,"abstract":"The work presented applies a statistical approach to study randomly distributed solder voids in MOSFET products. The grid size was varied as independent of the mesh element to account for typical void sizes observed in X-ray images. Thereafter the impact of random voids for different chip sizes was quantified. Results show that higher maximum chip temperatures can occur with voids located in the corner of the die. A simple analytical expression thereafter was developed to understand and explain this. Rth-JC (thermal resistance junction-to-case) and IR (infrared) measurements of selected test devices with known void distribution were performed as well. Measurement and simulated results were compared. In this work we attempt to establish a model for the evaluation of the process impact on Rth-JC. It also leads to some guidelines of solder joint inspection criteria for power devices.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121290843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromagnetic and circuital modeling of carbon nanotube interconnects","authors":"A. Maffucci, G. Miano, F. Villone","doi":"10.1109/ESTC.2008.4684497","DOIUrl":"https://doi.org/10.1109/ESTC.2008.4684497","url":null,"abstract":"This paper presents an electromagnetic and a circuit model to describe the propagation of electric signals along interconnects made by carbon nanotubes. The models are both derived from an enhanced fluid description of the carbon nanotube electrodynamics, which takes into account size effects disregarded in the literature. The electromagnetic model is obtained in a surface integral formulation by coupling the fluid equation to the full-wave Maxwell equations and is numerically solved using a null-pinv decomposition technique. The circuit model is derived within the frame of the classical multiconductor transmission line theory. Both the models are used to analyze case-studies of interest where the carbon nanotube technology is used to build electrical nano-interconnects.","PeriodicalId":146584,"journal":{"name":"2008 2nd Electronics System-Integration Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}