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High-speed epitaxial lift-off for III-V-on-insulator transistors on Si substrates 硅衬底上iii - v -on-绝缘体晶体管的高速外延提升
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804379
Sanghyeon Kim, Dae-Myeong Geum, S. Kim, Hyung-jun Kim, J. Song, W. Choi
{"title":"High-speed epitaxial lift-off for III-V-on-insulator transistors on Si substrates","authors":"Sanghyeon Kim, Dae-Myeong Geum, S. Kim, Hyung-jun Kim, J. Song, W. Choi","doi":"10.1109/S3S.2016.7804379","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804379","url":null,"abstract":"Thin body III-V-on-insulator (III-V-OI) structure is a promising device structure for future node transistors in CMOS technology. Typically, a direct wafer bonding (DWB) is used to fabricate III-V-OI on a Si substrate [1-3]. Donor wafers were etched out [1, 2] or separated by hydrogen implantation [3]. However, the former one is extremely costly and the latter one can induce the residual defects in the channel layer. Therefore, a cost-effective and non-destructive technology to fabricate III-V-OI becomes more important. On the other hand, an epitaxial lift-off (ELO), which splits donor wafer and device active layer by selective etching of sacrificial layer located between the two, is quite promising to meet the two requirements of low cost and defect issue [5]. However, conventional ELO needs a long processing time to etch thin sacrificial layer across the whole wafer as shown in Fig. 1. In this work, we developed high-speed ELO techniques via pre-patterning and surface hydrophilization and fabricated conceptual devices of GaAs-OI transistors.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Correlations between plasma induced damage and negative bias temperature instability in 65 nm bulk and thin-BOX FDSOI processes 等离子体诱导损伤与负偏置温度不稳定性在65nm块体和薄盒FDSOI工艺中的相关性
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804371
Ryo Kishida, Kazutoshi Kobayashi
{"title":"Correlations between plasma induced damage and negative bias temperature instability in 65 nm bulk and thin-BOX FDSOI processes","authors":"Ryo Kishida, Kazutoshi Kobayashi","doi":"10.1109/S3S.2016.7804371","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804371","url":null,"abstract":"We evaluate Plasma Induced Damage (PID) and Negative Bias Temperature Instability (NBTI) by measuring frequency of Ring Oscillators (ROs). Initial frequency degradation by PID from Antenna Ratio (AR) of 500 to 1k are 2.1% and 1.9% in the bulk and thin-BOX FDSOI, respectively. NBTI is accelerated by PID in less than 500 AR which is the upper limit of the antenna rule. NBTI correlates with PID and also with initial frequency. The correlation coefficient (CC) between NBTI-induced degradations and the initial frequency is 0.68 in FDSOI, while there is few correlation in bulk (CC = 0.24) because random dopant fluctuation is dominant.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114781508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Influence of source-drain engineering and temperature on split-capacitance characteristics of FDSOI p-i-n gated diodes 源漏工程和温度对FDSOI p-i-n门控二极管分容特性的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804373
K. Sasaki, C. Navarro, M. Bawedin, F. Andrieu, J. Martino, S. Cristoloveanu
{"title":"Influence of source-drain engineering and temperature on split-capacitance characteristics of FDSOI p-i-n gated diodes","authors":"K. Sasaki, C. Navarro, M. Bawedin, F. Andrieu, J. Martino, S. Cristoloveanu","doi":"10.1109/S3S.2016.7804373","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804373","url":null,"abstract":"Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi) are accurate, with error below 5%. At high temperature, the capacitance curves are narrower due to the threshold voltage (VT) lowering in n- and p-channels. However, the accuracy of tOX and tSi extraction is only marginally affected.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115468217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges and opportunities of vertical FET devices using 3D circuit design layouts 使用3D电路设计布局的垂直场效应管器件的挑战和机遇
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804409
A. Veloso, T. Huynh-Bao, E. Rosseel, V. Paraschiv, K. Devriendt, E. Vecchio, C. Delvaux, B. T. Chan, M. Ercken, Z. Tao, W. Li, E. Altamirano-Sanchez, J. Versluijs, S. Brus, P. Matagne, N. Waldron, J. Ryckaert, D. Mocuta, N. Collaert
{"title":"Challenges and opportunities of vertical FET devices using 3D circuit design layouts","authors":"A. Veloso, T. Huynh-Bao, E. Rosseel, V. Paraschiv, K. Devriendt, E. Vecchio, C. Delvaux, B. T. Chan, M. Ercken, Z. Tao, W. Li, E. Altamirano-Sanchez, J. Versluijs, S. Brus, P. Matagne, N. Waldron, J. Ryckaert, D. Mocuta, N. Collaert","doi":"10.1109/S3S.2016.7804409","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804409","url":null,"abstract":"We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114764127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing 基于细粒度体偏置的65nm SOTB功率可重构FPGA架构改进
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804400
M. Hioki, T. Katashita, H. Koike
{"title":"Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing","authors":"M. Hioki, T. Katashita, H. Koike","doi":"10.1109/S3S.2016.7804400","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804400","url":null,"abstract":"In the past, we developed 65nm SOTB power reconfigurable FPGAs by fine-grained body biasing composed of only elemental circuits such as LUT, DFF and MUX. This paper describes the architecture enhancements in the power reconfigurable FPGA including three key points such as the FPGA tile architecture optimization, reconfigurable clock gating scheme and 256kb RAM block implementation.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"641 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117097240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Transport in TriGate nanowire FET: Cross-section effect at the nanometer scale 三栅极纳米线场效应晶体管中的传输：纳米尺度的截面效应
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804374
J. Pelloux-Prayer, M. Cassé, S. Barraud, F. Triozon, Z. Zeng, Y. Niquet, J. Rouviere, G. Reimbold
{"title":"Transport in TriGate nanowire FET: Cross-section effect at the nanometer scale","authors":"J. Pelloux-Prayer, M. Cassé, S. Barraud, F. Triozon, Z. Zeng, Y. Niquet, J. Rouviere, G. Reimbold","doi":"10.1109/S3S.2016.7804374","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804374","url":null,"abstract":"We hereby present a study of electron mobility in Tri-gate SOI Nanowire (TGNW) transistors in a wide range of temperature from 20K up to 425K. We compared the temperature dependence for different values of the NW cross-section (width and height) and different crystallographic orientations of the conduction channel. We demonstrate that the electron mobility in narrow TGNWs is limited by surface roughness in the sidewall inversion surface whatever the NW orientation [110]/(100) or [100]/(100). We have also evidenced an enhanced temperature dependence, attributed to phonon scattering, as the cross-section of the NW decreases below a critical dimension (≈80nm).","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126279314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A radiation-hard layout structure to control back-gate biases in a 65 nm thin-BOX FDSOI process 65 nm薄盒FDSOI工艺中控制后门偏置的辐射硬布局结构
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804372
J. Yamaguchi, J. Furuta, Kazutoshi Kobayashi
{"title":"A radiation-hard layout structure to control back-gate biases in a 65 nm thin-BOX FDSOI process","authors":"J. Yamaguchi, J. Furuta, Kazutoshi Kobayashi","doi":"10.1109/S3S.2016.7804372","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804372","url":null,"abstract":"We propose a radiation-hard layout structure to control back-gate biases for thin-BOX FDSOI. The structure with fixed back-gate bias has strongest against soft errors, while the structure with P+ and N+ diffusions under power and ground rails makes flip-flops stronger against soft errors with back-gate bias controllability than the conventional structure without P+ and N+ diffusions. The test chip was fabricated by 65 nm bulk and thin-BOX FDSOI processes. The experimental results with α sources reveals that the structure with diffusions is effective to supress soft errors on the thin-BOX process. But it is not effective on the bulk process.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130365287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design, fabrication, and characterization of ultralow current operational-amplifier in the weak inversion mode in XFAB-XT018 technology 基于XFAB-XT018技术的弱反转超低电流运算放大器的设计、制造和特性研究
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804392
Farzin Akbar, Marco Ramsbeck, Elias Kogel
{"title":"Design, fabrication, and characterization of ultralow current operational-amplifier in the weak inversion mode in XFAB-XT018 technology","authors":"Farzin Akbar, Marco Ramsbeck, Elias Kogel","doi":"10.1109/S3S.2016.7804392","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804392","url":null,"abstract":"A 1.8V, 932 nA, rail-to-rail CMOS operational amplifier operating in the weak inversion regime in order to amplify the output signal of an air pressure sensor is presented. The two main parts of the ASIC are the beta-multiplier current source and the two stage amplifier. The layout has been drawn considering the matching techniques and the chip was fabricated and further characterized and measured.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134172601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling the impact of the vertical doping profile on FinFET SRAM VT mismatch 模拟垂直掺杂对FinFET SRAM VT失配的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804381
D. Burnett, Xusheng Wu, S. Mun, S. Pandey, M. Eller, S. Parihar, S. Samavedam
{"title":"Modeling the impact of the vertical doping profile on FinFET SRAM VT mismatch","authors":"D. Burnett, Xusheng Wu, S. Mun, S. Pandey, M. Eller, S. Parihar, S. Samavedam","doi":"10.1109/S3S.2016.7804381","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804381","url":null,"abstract":"The basic multi-gate Vt variation model for uniform doping is extended to support a 2-region fin doping methodology that provides good agreement with Vt mismatch measurements as well as useful insights into how the non-uniform fin doping impacts the mismatch. The methodology displays good agreement for both NMOS and PMOS SRAM devices from a FinFET process. The NMOS Vt mismatch as a function of Vt is found to follow the non-uniform doping model while the PMOS Vt mismatch is higher due to both high, non-uniform doping as well as P-metal gate workfunction induced mismatch.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost model for monolithic 3D integrated circuits 单片三维集成电路的成本模型
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804408
D. Gitlin, M. Vinet, F. Clermidy
{"title":"Cost model for monolithic 3D integrated circuits","authors":"D. Gitlin, M. Vinet, F. Clermidy","doi":"10.1109/S3S.2016.7804408","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804408","url":null,"abstract":"A cost model for monolithic 3D-ICs is presented that takes into account increased process complexity and associated yield impact as well as area reduction. The model enables more accurate PPC (Power, Performance and Cost) understanding and the range of applicability for monolithic 3D-IC technology. The model shows that depending on the die area and partitioning scheme, the cost benefit can be 50% or higher.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"159 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128900821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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