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2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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A 1.95GHz 28dBm fully integrated packaged power amplifier presenting a 3G FOM of 80 (PAE+ACLR) designed in H9SOIFEM CMOS 130nm: Development of an optimized high performances RF SOI power cell 一种采用H9SOIFEM CMOS 130nm设计的1.95GHz 28dBm全集成封装功率放大器，具有3G带宽80 (PAE+ACLR):开发一种优化的高性能RF SOI功率电池
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804390
V. Knopik, G. Bertrand, A. Monroy, S. Gachon, J. Morelle, P. Cathelin, B. Butaye
{"title":"A 1.95GHz 28dBm fully integrated packaged power amplifier presenting a 3G FOM of 80 (PAE+ACLR) designed in H9SOIFEM CMOS 130nm: Development of an optimized high performances RF SOI power cell","authors":"V. Knopik, G. Bertrand, A. Monroy, S. Gachon, J. Morelle, P. Cathelin, B. Butaye","doi":"10.1109/S3S.2016.7804390","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804390","url":null,"abstract":"A fully integrated and packaged Power Amplifier (PA) has been realized in 130nm STMicroelectronics H9SOIFEM. The PA is based on a new dedicated power cell delivering very good RF performances. At 28dBm output power, ACPR is -40dBc and PAE is 40%, reaching a FOM (ACPR+PAE) of 80 at 1.95GHz 3G standard, under 3.4V. Neither linearization nor efficiency enhancement technics have been used. The core power transistor provides very high power added efficiency (PAE) of 75% at a gain of 18dB typical, around 2GHz. This technology has been optimized for low cost RF front end module (FEM) applications.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131080972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of the crystal orientation on the operation of junctionless nanowire transistors 晶体取向对无结纳米线晶体管工作的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804380
R. Trevisoli, R. Doria, M. de Souza, M. Pavanello, S. Barraud, M. Vinet
{"title":"Influence of the crystal orientation on the operation of junctionless nanowire transistors","authors":"R. Trevisoli, R. Doria, M. de Souza, M. Pavanello, S. Barraud, M. Vinet","doi":"10.1109/S3S.2016.7804380","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804380","url":null,"abstract":"This work presents, for the first time, an analysis of the influence of the crystal orientation on the electrical performance of Junctionless Nanowire Transistors. Experimental results demonstrate that the device rotation from the standard <;110> to the <;100> direction over a (100) SOI wafer can significantly degrade the performance of the transistors.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low power highly linear temperature sensor based on SOI lateral PIN diodes 基于SOI横向PIN二极管的低功耗高线性温度传感器
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804382
M. de Souza, M. Pavanello, D. Flandre
{"title":"Low power highly linear temperature sensor based on SOI lateral PIN diodes","authors":"M. de Souza, M. Pavanello, D. Flandre","doi":"10.1109/S3S.2016.7804382","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804382","url":null,"abstract":"This work presents a highly linear temperature sensors implemented with SOI Lateral PIN Diodes, for low-power applications, biased on the exponential region of the I-V characteristics. Experimental results are shown for temperatures ranging between 150 K and 400 K, showing that depending on the selected bias currents, the linearity can be improved in comparison to a single SOI PIN diode. Simulations results show that the sensing range can be extended for both lower and higher temperatures maintaining high linearity.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory 具有竞争力的28纳米FDSOI技术1T-DRAM，用于低功耗嵌入式存储器
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804402
H. El Dirani, M. Bawedin, K. Lee, M. Parihar, X. Mescot, P. Fonteneau, P. Galy, F. Gámiz, Y.-T. Kim, P. Ferrari, S. Cristoloveanu
{"title":"Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory","authors":"H. El Dirani, M. Bawedin, K. Lee, M. Parihar, X. Mescot, P. Fonteneau, P. Galy, F. Gámiz, Y.-T. Kim, P. Ferrari, S. Cristoloveanu","doi":"10.1109/S3S.2016.7804402","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804402","url":null,"abstract":"We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z2-FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z2-FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration 在三维连续积分中保持层间互连稳定性的结活化的Ns激光退火
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804375
C. Fenouillet-Béranger, P. Acosta-Alba, B. Mathieu, S. Kerdilès, M.-P. Samson, B. Previtali, N. Rambal, V. Lapras, F. Ibars, A. Roman, R. Kachtouli, P. Besson, J. Nieto, L. Pasini, L. Brunet, F. Aussenac, J. Hartmann, F. Mazzamuto, I. Toqué-Trésonne, K. Huet, P. Batude, M. Vinet
{"title":"Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration","authors":"C. Fenouillet-Béranger, P. Acosta-Alba, B. Mathieu, S. Kerdilès, M.-P. Samson, B. Previtali, N. Rambal, V. Lapras, F. Ibars, A. Roman, R. Kachtouli, P. Besson, J. Nieto, L. Pasini, L. Brunet, F. Aussenac, J. Hartmann, F. Mazzamuto, I. Toqué-Trésonne, K. Huet, P. Batude, M. Vinet","doi":"10.1109/S3S.2016.7804375","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804375","url":null,"abstract":"In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 64 kb multi-threshold SRAM array with novel differential 8T bitcell in 32 nm SOI CMOS technology 基于32nm SOI CMOS技术的新型差分8T位元64kb多阈值SRAM阵列
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI: 10.1109/S3S.2016.7804388
Samira Ataei, J. Stine
{"title":"A 64 kb multi-threshold SRAM array with novel differential 8T bitcell in 32 nm SOI CMOS technology","authors":"Samira Ataei, J. Stine","doi":"10.1109/S3S.2016.7804388","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804388","url":null,"abstract":"An 8T SRAM bitcell is presented to improve the read stability and writability of SRAM in scaled technologies and low voltages. The presented bitcell achieves a faster access time by increasing the read current by 21% compared to a 6T bitcell. The proposed 8T bitcell utilizes a differential operation, single port and one wordline, therefore, it does not require any architectural changes from 6T SRAM architectures. Moreover, the effects of process-induced VTH variations in multi-threshold 8T bitcells are examined and it is shown that the choice for the best dual-threshold configuration of the proposed 8T bitcell varies due to trade-offs between access time, leakage-power and read/write stability under process variations. In addition, timing variations of the sense \"amplifier enable signal\" due to random process variations is reduced by using a Multi Replica Bitline Delay technique to decrease SRAM read access time. The proposed 8T bitcell is demonstrated in a 64 kb SRAM array in 32 nm SOI CMOS technology that operates at 2 GHz at 0.9 V and 250 MHz at 0.3 V.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126370193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes 低温运行对采用STI前后工艺制造的长通道应变Ge pfinfet的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/S3S.2016.7804384
Alberto V. de Oliveira, E. Simoen, Paula Ghedini Der Agopian, J. Martino, J. Mitard, L. Witters, N. Collaert, A. Thean, C. Claeys
{"title":"Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes","authors":"Alberto V. de Oliveira, E. Simoen, Paula Ghedini Der Agopian, J. Martino, J. Mitard, L. Witters, N. Collaert, A. Thean, C. Claeys","doi":"10.1109/S3S.2016.7804384","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804384","url":null,"abstract":"One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of InxGa1−x composition and source Zn diffusion temperature on intrinsic voltage gain in InGaAs TFETs InxGa1−x成分和源Zn扩散温度对InGaAs tfet本征电压增益的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/S3S.2016.7804393
C. Bordallo, J. Martino, P. Agopian, A. Alian, Y. Mois, R. Rooyackers, A. Vandooren, A. Verhulst, E. Simoen, C. Claeys, N. Collaert, A. Thean
{"title":"Impact of InxGa1−x composition and source Zn diffusion temperature on intrinsic voltage gain in InGaAs TFETs","authors":"C. Bordallo, J. Martino, P. Agopian, A. Alian, Y. Mois, R. Rooyackers, A. Vandooren, A. Verhulst, E. Simoen, C. Claeys, N. Collaert, A. Thean","doi":"10.1109/S3S.2016.7804393","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804393","url":null,"abstract":"This work reports for the first time on the experimental study of the intrinsic voltage gain of InGaAs nTFET. The influence of Indium/Gallium composition and Zn diffusion temperature is analyzed. For a higher Indium amount (In0.7Ga0.3As compared to In0.53Ga0.47As) the band to band tunneling (BTBT) is improved due to bandgap narrowing. A higher Zn diffusion temperature gives rise to a higher source doping, resulting in a smaller tunneling length, which also increases BTBT. In both devices the intrinsic voltage gain is improved. One interesting characteristic of these devices is that they present good analog performance at low voltages (VGS=VDS=0.6V), which is promising for low power/low voltage analog applications. High-temperature operation increases in all cases more the output conductance than the transconductance, resulting in a lower intrinsic voltage gain.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128251354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Back gate bias influence on SOI Ω-gate nanowire down to 10 nm width 后门偏置对SOI Ω-gate纳米线宽度减小至10 nm的影响
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/S3S.2016.7804394
L. Almeida, P. Agopian, J. Martino, S. Barraud, M. Vinet, O. Faynot
{"title":"Back gate bias influence on SOI Ω-gate nanowire down to 10 nm width","authors":"L. Almeida, P. Agopian, J. Martino, S. Barraud, M. Vinet, O. Faynot","doi":"10.1109/S3S.2016.7804394","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804394","url":null,"abstract":"We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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