High-speed epitaxial lift-off for III-V-on-insulator transistors on Si substrates

Thin body III-V-on-insulator (III-V-OI) structure is a promising device structure for future node transistors in CMOS technology. Typically, a direct wafer bonding (DWB) is used to fabricate III-V-OI on a Si substrate [1-3]. Donor wafers were etched out [1, 2] or separated by hydrogen implantation [3]. However, the former one is extremely costly and the latter one can induce the residual defects in the channel layer. Therefore, a cost-effective and non-destructive technology to fabricate III-V-OI becomes more important. On the other hand, an epitaxial lift-off (ELO), which splits donor wafer and device active layer by selective etching of sacrificial layer located between the two, is quite promising to meet the two requirements of low cost and defect issue [5]. However, conventional ELO needs a long processing time to etch thin sacrificial layer across the whole wafer as shown in Fig. 1. In this work, we developed high-speed ELO techniques via pre-patterning and surface hydrophilization and fabricated conceptual devices of GaAs-OI transistors.