{"title":"基于细粒度体偏置的65nm SOTB功率可重构FPGA架构改进","authors":"M. Hioki, T. Katashita, H. Koike","doi":"10.1109/S3S.2016.7804400","DOIUrl":null,"url":null,"abstract":"In the past, we developed 65nm SOTB power reconfigurable FPGAs by fine-grained body biasing composed of only elemental circuits such as LUT, DFF and MUX. This paper describes the architecture enhancements in the power reconfigurable FPGA including three key points such as the FPGA tile architecture optimization, reconfigurable clock gating scheme and 256kb RAM block implementation.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"641 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing\",\"authors\":\"M. Hioki, T. Katashita, H. Koike\",\"doi\":\"10.1109/S3S.2016.7804400\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the past, we developed 65nm SOTB power reconfigurable FPGAs by fine-grained body biasing composed of only elemental circuits such as LUT, DFF and MUX. This paper describes the architecture enhancements in the power reconfigurable FPGA including three key points such as the FPGA tile architecture optimization, reconfigurable clock gating scheme and 256kb RAM block implementation.\",\"PeriodicalId\":145660,\"journal\":{\"name\":\"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"641 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2016.7804400\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2016.7804400","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Architecture enhancements in 65nm SOTB power reconfigurable FPGA by fine-grained body biasing
In the past, we developed 65nm SOTB power reconfigurable FPGAs by fine-grained body biasing composed of only elemental circuits such as LUT, DFF and MUX. This paper describes the architecture enhancements in the power reconfigurable FPGA including three key points such as the FPGA tile architecture optimization, reconfigurable clock gating scheme and 256kb RAM block implementation.