Influence of source-drain engineering and temperature on split-capacitance characteristics of FDSOI p-i-n gated diodes

Abstract

Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi) are accurate, with error below 5%. At high temperature, the capacitance curves are narrower due to the threshold voltage (VT) lowering in n- and p-channels. However, the accuracy of tOX and tSi extraction is only marginally affected.