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Electrical Performance of Electronic Packaging - 2004最新文献

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SSN issues with IBIS models IBIS模型的SSN问题
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407554
A. Varma, Michael B. Steer, Paul D. Franzon
{"title":"SSN issues with IBIS models","authors":"A. Varma, Michael B. Steer, Paul D. Franzon","doi":"10.1109/EPEP.2004.1407554","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407554","url":null,"abstract":"A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS (input/output buffer information specification) models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University. IBIS model of the driver is also compared against model created using spline functions with finite time difference approximation modeling techniques. The three modeling techniques are analyzed for accuracy in modeling simultaneous switching noise in drivers.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129317792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A new modeling methodology for passive components based on black-box augmentation combined with equivalent circuit perturbation 一种基于等效电路扰动和黑盒增强的无源元件建模新方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407603
J. Kolstad, C. Blevins, J. Dunn, A. Weisshaar
{"title":"A new modeling methodology for passive components based on black-box augmentation combined with equivalent circuit perturbation","authors":"J. Kolstad, C. Blevins, J. Dunn, A. Weisshaar","doi":"10.1109/EPEP.2004.1407603","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407603","url":null,"abstract":"A new black-box augmentation methodology for broadband CAD modeling of interconnects and passive elements is presented. The new methodology is based on augmenting an existing equivalent circuit model with a black-box network described with rational polynomial functions while allowing perturbation of the equivalent circuit component values. The approach incorporates the accuracy of black-box modeling while simultaneously preserving the intuition that circuit designers obtain from a 'hand-engineered' equivalent circuit. Exemplary results are shown to illustrate the benefits and accuracy of the method.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128274588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Electrical validation of source synchronous chip-chip server links at 6.25 Gb/s 6.25 Gb/s源同步芯片-芯片服务器链路的电气验证
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407579
K. Canagasaby, S. Chaudhuri, S. Dabral
{"title":"Electrical validation of source synchronous chip-chip server links at 6.25 Gb/s","authors":"K. Canagasaby, S. Chaudhuri, S. Dabral","doi":"10.1109/EPEP.2004.1407579","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407579","url":null,"abstract":"Modeling and validation of 6.25 Gb/s source synchronous backplane links is demonstrated using a correlation methodology. The link model predictions correlate within 10-25% error against scope measured eye and using on-die scope eye when the transmitter output jitter, the interconnect loss and impedance profile and the transmitter equalizer is well modeled and correlated individually. In this paper, the link is assumed to have only transmitted side de-emphasis (equalization). The procedure get additional confidence, when the eye, created from the internal timing and voltage margins, correlates within 10-25% error to the predicted data pad eye. With these a reasonably scalable model over different topologies/speeds that can be used confidently for sensitivity analysis and predictions is obtained.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of current signatures for microprocessors 微处理器电流特征的表征
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407556
R. Weekly, S. Chun, F. O'Connell
{"title":"Characterization of current signatures for microprocessors","authors":"R. Weekly, S. Chun, F. O'Connell","doi":"10.1109/EPEP.2004.1407556","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407556","url":null,"abstract":"This work presents current signatures for a set of test cases running on a general purpose server IBM POWER5/spl trade/ processor under the control of IBM's AIX/spl trade/ operating system. This is part of activities focused on understanding how to optimize the power delivery infrastructure with respect to total system cost. Specifically a better understanding of the current signatures of processors coupled with better understanding of how to design the decoupling infrastructure and in what ways the processor circuits are susceptible to power domain voltage noise is expected to help us accomplish this.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"44 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131845285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A monolithic, compact balun/matching network for SiP applications 一个单片，紧凑的平衡/匹配网络的SiP应用程序
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407540
Robert C Frye, G. Badakere, Yaojian Lin, M. Pandi Chelvam
{"title":"A monolithic, compact balun/matching network for SiP applications","authors":"Robert C Frye, G. Badakere, Yaojian Lin, M. Pandi Chelvam","doi":"10.1109/EPEP.2004.1407540","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407540","url":null,"abstract":"We describe a circuit and design method for a compact balun/matching network suitable for a variety of RF application using thin-film integrated passive device (IPD) technology. The circuit uses resonant coupled inductors. By appropriate tuning of the capacitors in the circuit, the balun can be made to match a wide range of impedances. Measured results of example circuits for 802.11 b/g or Bluetooth applications (2.4-2.5 GHz) are presented, showing excellent agreement with simulation.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134354975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fast passivity enforcement for large and sparse macromodels 大型和稀疏宏模型的快速被动执行
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407600
Stefano Grivet-Talocia
{"title":"Fast passivity enforcement for large and sparse macromodels","authors":"Stefano Grivet-Talocia","doi":"10.1109/EPEP.2004.1407600","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407600","url":null,"abstract":"This work presents a fast technique for testing and enforcing passivity of linear macromodels characterized by a large and sparse structure. An optimized algorithm is proposed for the computation of the imaginary eigenvalues of the associated Hamiltonian matrix, which are iteratively perturbed until passivity is enforced. Each iteration of the proposed scheme requires a small computational cost that scales only linearly with the size of the problem.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133910141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system 微处理器系统供电网络阻抗的测量-建模相关性
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407592
K. Aygun, M. Hill, K.D. Ellert, K. Radhakrishnan
{"title":"Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system","authors":"K. Aygun, M. Hill, K.D. Ellert, K. Radhakrishnan","doi":"10.1109/EPEP.2004.1407592","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407592","url":null,"abstract":"An automated system for measuring the power delivery impedance profile on a functional system is presented. The data collected by this system is used to assess the accuracy of a distributed power delivery system model.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133956981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards 多gb /s差分印刷电路板中交流共模转换的建模与缓解
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407536
H. Heck, S. Hall, B. Horine, Tao Liang
{"title":"Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards","authors":"H. Heck, S. Hall, B. Horine, Tao Liang","doi":"10.1109/EPEP.2004.1407536","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407536","url":null,"abstract":"Techniques for quantifying and minimizing the impact of differential signal phase skew created by the non-homogeneous nature of FR4 PCBs are presented. Experimental results that allow modeling and simulation at multi-Gb/s signaling rates are developed and used to estimate the impact to voltage and timing margins at 5-10 Gb/s as a function of PCB trace length. A design approach for mitigating the impact is discussed, and results from a manufacturability study are used to assess the effectiveness of the approach.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Module placement for power supply noise and wire congestion avoidance in 3D packaging 3D封装中电源噪音和电线堵塞避免的模块放置
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407563
J. Minz, S. Lim, Jinwoo Choi, M. Swaminathan
{"title":"Module placement for power supply noise and wire congestion avoidance in 3D packaging","authors":"J. Minz, S. Lim, Jinwoo Choi, M. Swaminathan","doi":"10.1109/EPEP.2004.1407563","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407563","url":null,"abstract":"In this work, we present an automatic module placement algorithm for simultaneous power supply noise and routing congestion minimization for 3D packaging that are seriously threatening the performance and reliability of 3D packaging. We employ decoupling capacitance insertion for noise suppression and 3D global routing for congestion avoidance.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122428258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Are on-chip power-ground planes really needed? A signal integrity perspective 芯片上的电源-地平面真的需要吗?信号完整性视角
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407618
I. Elfadel, P. Feldmann, H. Chen, D. Ostapko
{"title":"Are on-chip power-ground planes really needed? A signal integrity perspective","authors":"I. Elfadel, P. Feldmann, H. Chen, D. Ostapko","doi":"10.1109/EPEP.2004.1407618","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407618","url":null,"abstract":"We use the on-chip bus characterization methodology of to study the impact of the on-chip power distribution system on the signal integrity of a 12-line bus. We compare two power supply systems implemented in the same Cu BEOL stack: an entirely grid-based system and a system similar to in that it contains one metal layer dedicated to V/sub dd/ and one metal layer dedicated to V/sub ss/. We show that while the dedicated power/ground layers do contribute to the mitigation of the inductive and return-path impedance effects, the ultimate signal integrity of the on-chip bus depends on the interplay between resistive losses, electromagnetic couplings (capacitive and inductive), and the driving and receiving circuitry.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122524425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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