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Electrical Performance of Electronic Packaging - 2004最新文献

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Application of domain decomposition to the finite-element electromagnetic modeling of planar multi-layered interconnect structures & integrated passives 区域分解在平面多层互连结构及集成无源有限元电磁建模中的应用
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407610
Hong Wu, A. Cangellaris, A. Kuo
{"title":"Application of domain decomposition to the finite-element electromagnetic modeling of planar multi-layered interconnect structures & integrated passives","authors":"Hong Wu, A. Cangellaris, A. Kuo","doi":"10.1109/EPEP.2004.1407610","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407610","url":null,"abstract":"A domain-decomposition assisted finite element modeling methodology is implemented for broadband electromagnetic modeling of multilayered interconnects and integrated passives. The proposed methodology is aimed at tackling the modeling complexity of the high-density multi-layer signal wiring environment encountered in state-of-the-art packages for high-speed digital and mixed-signal integrated circuits.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134318756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modeling requirements for transmission lines in multi-gigabit systems 多千兆系统中传输线的建模要求
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407549
S. Hall, Tao Uang, H. Heck, D. Shykind
{"title":"Modeling requirements for transmission lines in multi-gigabit systems","authors":"S. Hall, Tao Uang, H. Heck, D. Shykind","doi":"10.1109/EPEP.2004.1407549","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407549","url":null,"abstract":"As computer clock speeds continue to increase at a rate dictated by Moore's Law, the system buses must also scale in proportion to the processor speed. As data rates approach 8 to 10 Gb/s, the traditional methods used to model transmission lines start to break down and become inadequate for the proper prediction of signal integrity. Specifically, the approximations made in traditional transmission line models, while perfectly adequate for slower speeds, violate conservation of energy principles and produce non-causal waveforms in the time domain responses. This work is discuss the problems associated with accurately predicting transient responses at multi-gigabit data rates and provide a simple and practical solution that accurately predicts transient responses for multi-gigabit channel design.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Modeling of semiconductor substrate on on-chip power grid switching 片上电网开关上半导体衬底的建模
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407606
J. Ihm, A. Cangellaris
{"title":"Modeling of semiconductor substrate on on-chip power grid switching","authors":"J. Ihm, A. Cangellaris","doi":"10.1109/EPEP.2004.1407606","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407606","url":null,"abstract":"A methodology is proposed and demonstrated for the modeling of the semiconductor substrate on on-chip power grid switching. A comprehensive electromagnetic model for the power grid, founded on the finite-difference approximation of Maxwell's curl equations, is combined with properly constructed, frequency-dependent equivalent surface impedance models for the doped semiconductor substrate to capture the impact of substrate loss on the grid response during switching. Numerical studies are utilized to illustrate the capabilities of the developed on-chip power grid solver.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114698216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A model for on-chip decoupling capacitor effectiveness including gate leakage effects 考虑栅极泄漏效应的片上去耦电容效能模型
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407616
J. Rius, M. Meijer
{"title":"A model for on-chip decoupling capacitor effectiveness including gate leakage effects","authors":"J. Rius, M. Meijer","doi":"10.1109/EPEP.2004.1407616","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407616","url":null,"abstract":"This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A robust physical model extraction method for a memory device with differential routed package traces 一种具有差分封装路径的存储器件的鲁棒物理模型提取方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407566
H. Shi, W. Beyene, X. Yuan
{"title":"A robust physical model extraction method for a memory device with differential routed package traces","authors":"H. Shi, W. Beyene, X. Yuan","doi":"10.1109/EPEP.2004.1407566","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407566","url":null,"abstract":"To quantify the impact of device parasitics on the performance and yield of high-speed systems, a reliable procedure for parasitic extraction and characterization needs to be established. A robust physical model extraction method of silicon parasitic is developed for a 3.2 Gbps memory device with differentially routed package traces. This method employs parasitic models that directly correlate to the physical features in the PCB, fixture, package, and the active device under proper voltage biases. Measurements are performed using a vector network analyzer (VNA) and a differential time-domain reflectometry (TDR). The standard two-port S-parameters are converted to the mixed-mode S-parameters, i.e., odd and even mode S-parameters. The model parameters of the parasitics are then extracted through the minimization of the difference between the simulated and the measured odd-mode S-parameters. Measured TDR results, such as package impedance and on-die termination resistance, are used to constrain the variables and optimization range. This method is applied to the parasitic extraction of an actual device to demonstrate its accuracy and robustness.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient SPICE macromodel for EMI analysis of electronic packages and high-speed interconnects 用于电子封装和高速互连的电磁干扰分析的高效SPICE宏模型
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407609
G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis, I. Erdin
{"title":"Efficient SPICE macromodel for EMI analysis of electronic packages and high-speed interconnects","authors":"G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis, I. Erdin","doi":"10.1109/EPEP.2004.1407609","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407609","url":null,"abstract":"This work presents a SPICE macromodel for fast transient analysis of lossy multiconductor transmission line (MTL) interconnects in the presence of electromagnetic interference (EMI). A simplified formulation based on split representation at both ends of the MTL structure for computation of equivalent sources in the time-domain is described. A passive and compact macromodel based on delay extraction and closed-form representation is used to describe the distributed nature of the MTL stamp. The proposed algorithm, while guaranteeing the stability of the simulation by employing passive macromodels, provides significant speed-up for EMI analysis of transmission line networks, especially with large delay and low losses.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128266526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
How detrimental could a via be? via的危害有多大?
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407555
L. Shan, Y. Kwark, D. Dreps, J. Trewhella
{"title":"How detrimental could a via be?","authors":"L. Shan, Y. Kwark, D. Dreps, J. Trewhella","doi":"10.1109/EPEP.2004.1407555","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407555","url":null,"abstract":"The vertical interconnects used in printed circuit boards, known as vias, are becoming increasingly critical to interconnect performance with ever increasing system data rates. To explore the effects of vias on system link performance, both simulations and measurements on test structures were implemented in a wide frequency range. The results indicate that proper via management is vital to the success of interconnect designs operating at multi-Gb/s data rates.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121644249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-end server system partitioning for cost reduction 用于降低成本的高端服务器系统分区
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407528
G. Katopis, T. Zhou
{"title":"High-end server system partitioning for cost reduction","authors":"G. Katopis, T. Zhou","doi":"10.1109/EPEP.2004.1407528","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407528","url":null,"abstract":"In this work finite dimension integer programming for 2-core and 3-core chip designs is used to define the optimum number of processors in a SMP node (symmetric multi-processing) from the point of view of minimizing the number of the chips that cannot be used in the system even if they have functionally good PU cores on them. In effect the trade-offs between the PU cores on a chip, the number of PU on an SMP node, and the cost of the chip are studied. It is asserted that to the first order the cost of the chips is proportional to the scrap of chips with good cores on them that cannot be used in the implementation of the SMP nodes. The model shows that an optimized SMP offering can be defined so that the total chip cost of high-end server system can be reduced. This desired cost reduction limits the SMP node size for a given processor chip yield. It is shown that as the chip yields are improved, the SMP node size that can be profitably implemented can also be increased.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114417772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Isolation in mixed-signal systems using a novel electromagnetic bandgap (EBG) structure 采用新型电磁带隙(EBG)结构的混合信号系统隔离
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407585
Jinwoo Choi, V. Govind, M. Swaminathan, L. Wan, R. Doraiswami
{"title":"Isolation in mixed-signal systems using a novel electromagnetic bandgap (EBG) structure","authors":"Jinwoo Choi, V. Govind, M. Swaminathan, L. Wan, R. Doraiswami","doi":"10.1109/EPEP.2004.1407585","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407585","url":null,"abstract":"This work presents an efficient isolation method in mixed-signal systems using a novel electromagnetic bandgap (EBG) structure called the alternating impedance EBG (AI-EBG) for isolating sensitive RF/analog circuits from noisy digital circuits. This EBG structure shows excellent isolation by suppressing almost all possible electromagnetic modes in bandgap frequencies. Measurements on a practical mixed-signal system show the feasibility of using this EBG structure to reduce noise coupling between RF/analog circuits and digital circuits, especially where a common power supply is used. To the best of our knowledge, this is the first example of a realistic mixed-signal system employing an EBG-based noise suppression scheme.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A global router for system-on-package targeting layer and crosstalk minimization 用于系统级包目标层和串扰最小化的全局路由器
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407557
J. Minz, S. Lim
{"title":"A global router for system-on-package targeting layer and crosstalk minimization","authors":"J. Minz, S. Lim","doi":"10.1109/EPEP.2004.1407557","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407557","url":null,"abstract":"We formulate and solve a new 3D global routing problem for system-on-package. Our divide-and-conquer algorithm provides an effective way to decompose the complex 3D problem into a set of 2D problems for simultaneous layer and crosstalk minimization.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117222086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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