考虑栅极泄漏效应的片上去耦电容效能模型

Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI:10.1109/EPEP.2004.1407616

J. Rius, M. Meijer

{"title":"考虑栅极泄漏效应的片上去耦电容效能模型","authors":"J. Rius, M. Meijer","doi":"10.1109/EPEP.2004.1407616","DOIUrl":null,"url":null,"abstract":"This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A model for on-chip decoupling capacitor effectiveness including gate leakage effects\",\"authors\":\"J. Rius, M. Meijer\",\"doi\":\"10.1109/EPEP.2004.1407616\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.\",\"PeriodicalId\":143349,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging - 2004\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging - 2004\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2004.1407616\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging - 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2004.1407616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文提出了一种包含栅极隧穿电流的片上去耦电容器模型。该模型表明，集总模型在高频处失效，必须用分布式模型代替。它还显示了栅极泄漏如何降低这种封盖在低频率和高频率下的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A model for on-chip decoupling capacitor effectiveness including gate leakage effects

This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.

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Electrical Performance of Electronic Packaging - 2004

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