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Electrical Performance of Electronic Packaging - 2004最新文献

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A novel pair-based (2/spl times/2) technique for fast inductance extraction of narrow on-chip interconnects 一种基于对(2/spl倍/2)的窄片上互连快速电感提取技术
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407620
S. Chakravarthy, M. Mazumder, C. Dai
{"title":"A novel pair-based (2/spl times/2) technique for fast inductance extraction of narrow on-chip interconnects","authors":"S. Chakravarthy, M. Mazumder, C. Dai","doi":"10.1109/EPEP.2004.1407620","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407620","url":null,"abstract":"Inductance noise coupling to a net primarily depends on the mutual inductances between the net and its attackers. The mutual inductances between the attackers themselves are assumed to have less impact, and are consequently ignored in some noise estimation methodologies for post-layout extraction flows. Such simplified methodologies do not require the fully coupled inductance matrix; and it rather needs only the self-inductance of the attackers and a mutual inductance between the victim and its attackers. A new technique has been implemented to achieve an average speed up of 10/spl times/ with an accuracy loss of less than +/- 5% with respect to the full (N/spl times/N) extraction.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124931460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate analysis of multi-layered signal and power distributions using the fringe RLGC models 利用条纹RLGC模型精确分析多层信号和功率分布
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407558
Ching-Chao Huang, C. Luk
{"title":"Accurate analysis of multi-layered signal and power distributions using the fringe RLGC models","authors":"Ching-Chao Huang, C. Luk","doi":"10.1109/EPEP.2004.1407558","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407558","url":null,"abstract":"This work introduces the fringe RLGC (i.e., resistance, inductance, conductance, and capacitance) models to accurately compute the broadband S parameters for not only large power planes but also thin signal traces in multi-layered package and PCB environments. With comparable accuracy and 100/spl times/ faster than a 3D full-wave field solver, this technique enables ultra-fast design iterations to optimize the layouts for insertion and return losses, resonance frequencies, and placement of decoupling capacitors, etc.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"392 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114915023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integrated power supply frequency domain impedance meter (IFDIM) 集成电源频域阻抗计(IFDIM)
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407591
A. Waizman, M. Livshitz, M. Sotman
{"title":"Integrated power supply frequency domain impedance meter (IFDIM)","authors":"A. Waizman, M. Livshitz, M. Sotman","doi":"10.1109/EPEP.2004.1407591","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407591","url":null,"abstract":"IFDIM is an integrated and self-checking on-die current throttling method that accurately measures CPU's power delivery impedance profile from the die up to the voltage regulator. Impedance profile characterization in 100Hz-600MHz frequency ranges is demonstrated.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Broadband characterization of miniaturized on-chip differential circuits using G-S-G probe 用G-S-G探针研究微型化片上差分电路的宽带特性
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407567
Hung-Ta Tso, C. Kuo
{"title":"Broadband characterization of miniaturized on-chip differential circuits using G-S-G probe","authors":"Hung-Ta Tso, C. Kuo","doi":"10.1109/EPEP.2004.1407567","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407567","url":null,"abstract":"An approach is presented to characterize on-chip differential coplanar-strip-line (CPS) test circuits using G-S-G probes. This probe convert signal from either a coaxial connector or waveguide into the test circuit under test to achieve impedance matching and field pattern matching. With a symmetric duplicate of the test circuit in shunt connection, the circuit can be characterized over a wide frequency range. This method is especially effective to miniaturized circuits. A 40-GHz silicon-based filter is employed for demonstration.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129837967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement based multi-port models for HSS link channel coupling 基于测量的HSS链路通道耦合多端口模型
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407547
Jiang Li, C. Parker
{"title":"Measurement based multi-port models for HSS link channel coupling","authors":"Jiang Li, C. Parker","doi":"10.1109/EPEP.2004.1407547","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407547","url":null,"abstract":"Measurement-based multi-port (/spl ges/8) s-parameter models are developed for HSS links. These models provide wide-bandwidth and large number of ports for worst-case differential coupling simulations even when the test vehicles have only limited accessibility.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123617708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Error factors in transmission line analysis with 3-dimensional electromagnetic field simulations 三维电磁场仿真分析传输线误差因素
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407573
H. Kubota, T. Watanabe, K. Araki, H. Asai
{"title":"Error factors in transmission line analysis with 3-dimensional electromagnetic field simulations","authors":"H. Kubota, T. Watanabe, K. Araki, H. Asai","doi":"10.1109/EPEP.2004.1407573","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407573","url":null,"abstract":"In this work, the accuracy of FDTD simulation by the comparison of S-parameters, which are obtained by FDTD method and experimental measurement in the analysis of the printed circuit boards with simple structured signal line. In comparison of S-parameters of signal lines, the disparity occurred from cell size is regarded as the mismatch of the characteristic impedance of the modeled signal lines. An attempt is made to decide the adequate cell size by estimation of the characteristic impedance based on finite difference method (FDM). In addition, an efficient technique to compensate the characteristic impedance is described. It is expected that this study is useful for the verification of signal integrity.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134513310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IBM Power5 bus designs for on- and off-module connections IBM Power5总线设计用于开模块和关模块连接
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407577
D. Dreps, F. Ferraiolo, A. Haridass, R. Reese, J. Schiff, B. Truong
{"title":"IBM Power5 bus designs for on- and off-module connections","authors":"D. Dreps, F. Ferraiolo, A. Haridass, R. Reese, J. Schiff, B. Truong","doi":"10.1109/EPEP.2004.1407577","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407577","url":null,"abstract":"This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133964550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Device macromodel impact on data link performance assessment 设备宏模型对数据链路性能评估的影响
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407598
I. Stievano, I. Maio, F. Canavero, C. Siviero
{"title":"Device macromodel impact on data link performance assessment","authors":"I. Stievano, I. Maio, F. Canavero, C. Siviero","doi":"10.1109/EPEP.2004.1407598","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407598","url":null,"abstract":"The use of simulation and macromodels to assess the performance of a typical interconnecting system is addressed. A receiver macromodel including threshold decision of received signals is proposed, and an efficiency analysis demonstrates that the use of well-designed macromodels for all parts of the transmission chain dramatically speeds up the simulation. A careful discussion of simulated eye diagrams shows that macromodels guarantee timing accuracy even in very long bit sequences.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power delivery modeling and design methodology for a programmable logic device package 可编程逻辑器件封装的功率传输建模与设计方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407561
A. Pannikkat, J. Long, Jin Zhao
{"title":"Power delivery modeling and design methodology for a programmable logic device package","authors":"A. Pannikkat, J. Long, Jin Zhao","doi":"10.1109/EPEP.2004.1407561","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407561","url":null,"abstract":"A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Transient current extraction from time domain voltage measurement 时域电压测量的瞬态电流提取
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407572
Y. Zhou, B. Herberg
{"title":"Transient current extraction from time domain voltage measurement","authors":"Y. Zhou, B. Herberg","doi":"10.1109/EPEP.2004.1407572","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407572","url":null,"abstract":"An easy method to extract the current signature of a core power supply is suggested and to measure the impedance of the PDS and the voltage at the interface of interest. With modern electromagnetic simulation tools such as SPEED2000 the impedance measurement of the PDS can be eliminated, replaced by a simple time domain simulation. It is used to obtain the transient current during HRESET of a microprocessor system.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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