D. Dreps, F. Ferraiolo, A. Haridass, R. Reese, J. Schiff, B. Truong
{"title":"IBM Power5总线设计用于开模块和关模块连接","authors":"D. Dreps, F. Ferraiolo, A. Haridass, R. Reese, J. Schiff, B. Truong","doi":"10.1109/EPEP.2004.1407577","DOIUrl":null,"url":null,"abstract":"This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"IBM Power5 bus designs for on- and off-module connections\",\"authors\":\"D. Dreps, F. Ferraiolo, A. Haridass, R. Reese, J. Schiff, B. Truong\",\"doi\":\"10.1109/EPEP.2004.1407577\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.\",\"PeriodicalId\":143349,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging - 2004\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging - 2004\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2004.1407577\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging - 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2004.1407577","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
IBM Power5 bus designs for on- and off-module connections
This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.