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Electrical Performance of Electronic Packaging - 2004最新文献

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Fast capacitance extraction using inexact factorization 使用非精确分解的快速电容提取
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407611
Shu Yan, V. Sarin, Weiping Shi
{"title":"Fast capacitance extraction using inexact factorization","authors":"Shu Yan, V. Sarin, Weiping Shi","doi":"10.1109/EPEP.2004.1407611","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407611","url":null,"abstract":"Most capacitance extraction algorithms based on boundary element method (BEM) use iterative solvers, which is favorable for solving large systems. Different from the common practice, we present an approach that solves a small system for capacitance using the direct solver. Our study is based on the sparse formulation proposed in. With proper ordering of the rows and columns, the sparse system can be approximated by its inexact factorization. Furthermore, with the proper ordering, the part of the solution vector, which contributes to capacitance, can be solved using the sub-matrix of the inexact factors. The dimension of the sub-matrix is O(m), where m is the number of conductors. To our knowledge, this is the first BEM style method to solve capacitance extraction problem without using iterative solver. Experimental results show that the new algorithm is up to 100 times faster than FastCap and is also much faster than the method in (we call it PHiCap). The error of the new method with respect to FastCap is within 2%.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116062030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On-chip global signaling by wave pipelining 芯片上的全局信号的波流水线
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407619
M. Hashimoto, A. Tsuchiya, H. Onodera
{"title":"On-chip global signaling by wave pipelining","authors":"M. Hashimoto, A. Tsuchiya, H. Onodera","doi":"10.1109/EPEP.2004.1407619","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407619","url":null,"abstract":"This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122886093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Simultaneous switching noise analysis for full-chip power integrity sign-off 同时开关噪声分析全芯片电源完整性签字
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407559
M. Schmitt, Yu Liu, N. Chang
{"title":"Simultaneous switching noise analysis for full-chip power integrity sign-off","authors":"M. Schmitt, Yu Liu, N. Chang","doi":"10.1109/EPEP.2004.1407559","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407559","url":null,"abstract":"This work describes an efficient methodology for the analysis of simultaneous switching noise in an integrated system of a microchip in its package and board environment. This methodology has been used to analyze and identify the noise from I/O cell simultaneous switching output (I/O SSO) on a large network processor design in 130 nm technology. This methodology provides a fast and accurate global I/O SSO analysis that can be applied during the design phase to identify I/O SSO effects and their impact on the core. The supply noise predicted by the I/O SSO analysis was correlated with full-chip results of a true dynamic AC noise analysis flow and verified with measurements on silicon.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128884498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A comparison of performance potentials of single ended vs. differential signaling 单端与差分信号的性能潜力比较
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407580
Zhaoqing Chen, G. Katopis
{"title":"A comparison of performance potentials of single ended vs. differential signaling","authors":"Zhaoqing Chen, G. Katopis","doi":"10.1109/EPEP.2004.1407580","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407580","url":null,"abstract":"The performance comparison of single ended and differential signaling of 10-40Gb/s is documented here with an interconnect distance of 12-20 mm on a high loss first level packaging structure. The comparison was based on eye diagrams by circuit simulators using multi-coupled transmission line models with frequency-dependent RLGC parameters.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132045152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Parallel plate slot coupler modeling using two dimensional frequency domain transmission line matrix method 平行板槽耦合器的二维频域传输线矩阵建模方法
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407541
R. Ito
{"title":"Parallel plate slot coupler modeling using two dimensional frequency domain transmission line matrix method","authors":"R. Ito","doi":"10.1109/EPEP.2004.1407541","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407541","url":null,"abstract":"A slot coupler for coupling between via-defined waveguides is analyzed using the 2D frequency domain transmission line matrix (2D-TLM) method. The general 2D-TLM model for a slot coupling between parallel plate waveguides is useful in the design of advanced low cost millimeter-wave packaging. The via waveguide coupler is modeled and the model verified by comparison to measurement.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127782398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Modeling of power distribution networks with retardation using the transmission matrix method 用传输矩阵法对有延迟的配电网进行建模
Electrical Performance of Electronic Packaging - 2004 Pub Date : 2004-10-25 DOI: 10.1109/EPEP.2004.1407595
T. Watanabe, K. Srinivasan, H. Asai, M. Swaminathan
{"title":"Modeling of power distribution networks with retardation using the transmission matrix method","authors":"T. Watanabe, K. Srinivasan, H. Asai, M. Swaminathan","doi":"10.1109/EPEP.2004.1407595","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407595","url":null,"abstract":"This work describes the analysis of multilayered power distribution networks that include signal lines and vias. The signal lines are modeled as transmission lines, and vias are represented as not only self and mutual inductances but also include retardation currents. The structures have been analyzed using the transmission matrix method (TMM) in the frequency domain. Analysis using the TMM provides considerable savings in memory compared to SPICE.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114915150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Compact broadband resistance model for microstrip transmission lines 微带传输线的紧凑型宽带电阻模型
Electrical Performance of Electronic Packaging - 2004 Pub Date : 1900-01-01 DOI: 10.1109/EPEP.2004.1407553
J. Balachandran, S. Brebels, G. Carchon, W. De Raedt, B. Nauwelaers, E. Beyne
{"title":"Compact broadband resistance model for microstrip transmission lines","authors":"J. Balachandran, S. Brebels, G. Carchon, W. De Raedt, B. Nauwelaers, E. Beyne","doi":"10.1109/EPEP.2004.1407553","DOIUrl":"https://doi.org/10.1109/EPEP.2004.1407553","url":null,"abstract":"This work presents a closed form broadband resistance model for microstrip transmission lines. The proposed model is compact and scalable, and is within 7% of experimental values. The model uses a non-discontinuous analytical function valid in all bands ranging from DC to microwave frequencies.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114451417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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