{"title":"芯片上的全局信号的波流水线","authors":"M. Hashimoto, A. Tsuchiya, H. Onodera","doi":"10.1109/EPEP.2004.1407619","DOIUrl":null,"url":null,"abstract":"This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"On-chip global signaling by wave pipelining\",\"authors\":\"M. Hashimoto, A. Tsuchiya, H. Onodera\",\"doi\":\"10.1109/EPEP.2004.1407619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.\",\"PeriodicalId\":143349,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging - 2004\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging - 2004\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2004.1407619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging - 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2004.1407619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.