Simultaneous switching noise analysis for full-chip power integrity sign-off

Abstract

This work describes an efficient methodology for the analysis of simultaneous switching noise in an integrated system of a microchip in its package and board environment. This methodology has been used to analyze and identify the noise from I/O cell simultaneous switching output (I/O SSO) on a large network processor design in 130 nm technology. This methodology provides a fast and accurate global I/O SSO analysis that can be applied during the design phase to identify I/O SSO effects and their impact on the core. The supply noise predicted by the I/O SSO analysis was correlated with full-chip results of a true dynamic AC noise analysis flow and verified with measurements on silicon.