{"title":"可编程逻辑器件封装的功率传输建模与设计方法","authors":"A. Pannikkat, J. Long, Jin Zhao","doi":"10.1109/EPEP.2004.1407561","DOIUrl":null,"url":null,"abstract":"A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.","PeriodicalId":143349,"journal":{"name":"Electrical Performance of Electronic Packaging - 2004","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Power delivery modeling and design methodology for a programmable logic device package\",\"authors\":\"A. Pannikkat, J. Long, Jin Zhao\",\"doi\":\"10.1109/EPEP.2004.1407561\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.\",\"PeriodicalId\":143349,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging - 2004\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging - 2004\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2004.1407561\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging - 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2004.1407561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power delivery modeling and design methodology for a programmable logic device package
A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.