Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards

Abstract

Techniques for quantifying and minimizing the impact of differential signal phase skew created by the non-homogeneous nature of FR4 PCBs are presented. Experimental results that allow modeling and simulation at multi-Gb/s signaling rates are developed and used to estimate the impact to voltage and timing margins at 5-10 Gb/s as a function of PCB trace length. A design approach for mitigating the impact is discussed, and results from a manufacturability study are used to assess the effectiveness of the approach.