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8Gbps CMOS ASK modulator for 60GHz wireless communication 用于60GHz无线通信的8Gbps CMOS ASK调制器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708745
A. Oncu, K. Takano, M. Fujishima
{"title":"8Gbps CMOS ASK modulator for 60GHz wireless communication","authors":"A. Oncu, K. Takano, M. Fujishima","doi":"10.1109/ASSCC.2008.4708745","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708745","url":null,"abstract":"In this paper we present a millimeter-wave CMOS amplitude-shift-keying (ASK) modulator for 60 GHz wireless communication at greater than 1 Gbps. It is designed using shunt NMOSFET switches between the signal and the ground line of a transmission line. A reduced-switch architecture is used to achieve high speed. The transmission line length between switches is adjusted to achieve high isolation with a reduced number of switches. A 60 GHz millimeter-wave ASK modulator is successfully realized by using a 6-metal 1-poly 90 nm CMOS process. The size of the chip is 0.8 mm times 0.48 mm including the pads. The core size is 0.61 mm times 0.3 mm. The isolation and maximum data rate of the modulator at 60 GHz are measured to be 26.6 dB and 8 Gbps, respectively. The product of the maximum data rate and the isolation of this modulator is 170 GHz, which is the highest value among over-Gbps ASK modulators.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126476716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Differential-drive CMOS rectifier for UHF RFIDs with 66% PCE at −12 dBm Input 差分驱动CMOS整流器用于UHF rfid与66% PCE在−12 dBm输入
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708740
A. Sasaki, K. Kotani, T. Ito
{"title":"Differential-drive CMOS rectifier for UHF RFIDs with 66% PCE at −12 dBm Input","authors":"A. Sasaki, K. Kotani, T. Ito","doi":"10.1109/ASSCC.2008.4708740","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708740","url":null,"abstract":"A high efficiency differential CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. Differential-drive topology enables simultaneous low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency(PCE), especially under small RF input power conditions. The differential-drive rectifier was fabricated with 0.18-mum CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on an input RF signal frequency and output loading conditions was also evaluated. 66% of PCE was achieved under conditions of 953 MHz, -12 dBm RF input and 10 KOmega DC output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121529382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
A CMOS detector system for fluorescent bio-sensing application 用于荧光生物传感的CMOS探测器系统
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708795
Nan Liu, Zhiliang Hong, Ran Liu
{"title":"A CMOS detector system for fluorescent bio-sensing application","authors":"Nan Liu, Zhiliang Hong, Ran Liu","doi":"10.1109/ASSCC.2008.4708795","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708795","url":null,"abstract":"This system integrates a CMOS process compatible photodiode, a low noise capacitive trans-impedance amplifier (CTIA) and a 12-bit pipelined analog-to-digital converter (ADC). The chip fabricated in a 0.18-mum standard CMOS technology occupies 3 MMZ and consumes 37 mW. Experimental results show that the Nwell/Psub photodiode used in the fluorescent detecting experiment has a sensitivity of 0.1 A/W at 515 nm and a dark current of 3 nA/cm2. The maximum differential and integral nonlinearity of the designed ADC are +0.8 LSB and -3 LSB, respectively. With a solution volume of 0.5 mul, the detector system is able to detect the fluorescein solution concentration as low as 625 ng/ml. The minimum detectable fluorescent intensity and photocurrent are 18 nW/cm2 and 36 fA, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.12pJ/b resonance compensated inductive transceiver with a fault-tolerant network controller for wearable body sensor networks 一种带容错网络控制器的1.12pJ/b谐振补偿电感收发器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708790
J. Yoo, Seulki Lee, H. Yoo
{"title":"A 1.12pJ/b resonance compensated inductive transceiver with a fault-tolerant network controller for wearable body sensor networks","authors":"J. Yoo, Seulki Lee, H. Yoo","doi":"10.1109/ASSCC.2008.4708790","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708790","url":null,"abstract":"A low-energy inductive coupling link with a low energy fault-tolerant wearable body sensor network (BSN) controller is proposed to realize intra- and cross-layer wearable network at once. The intra-layer switch adopts the hybrid routing scheme to achieve fault-tolerance, and the cross-layer inductive transceiver employs the resonance compensator with an on-chip capacitor bank and a variable hysteresis Schmitt-Trigger to compensate dynamic and static variances of an woven inductor, achieving 10 Mbps wireless transaction with the reception energy of 1.12pJ/b at 2.5 V supply in 0.25 mum 1P5M CMOS.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117349563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A wireless real-time on-chip bus trace system using quasi-synchronous parallel inductive coupling transceivers 一种采用准同步并行电感耦合收发器的无线实时片上总线跟踪系统
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708742
S. Kawai, T. Ikari, Y. Takikawa, H. Ishikuro, T. Kuroda
{"title":"A wireless real-time on-chip bus trace system using quasi-synchronous parallel inductive coupling transceivers","authors":"S. Kawai, T. Ikari, Y. Takikawa, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2008.4708742","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708742","url":null,"abstract":"A 480 Mb/s wireless real-time bus trace system with a pulse-based inductive coupling channel array was developed using an 0.25 mum CMOS process. The size and pitch of the inductor array are determined by numerical calculation to optimize the tradeoff between the channel coupling, crosstalk, and alignment tolerance. A low-power quasi-synchronous system is proposed to obtain an enough timing margin for RX pulse detection under the presence of the clock skew. Power consumption is scalable to the data rate in this system.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132634050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Foundry-fabless collaboration for semiconductor SoC industry in Korea 韩国半导体SoC产业的无晶圆代工厂合作
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708714
Y. Oh, Y. Lee, Jae Song, T. Kim
{"title":"Foundry-fabless collaboration for semiconductor SoC industry in Korea","authors":"Y. Oh, Y. Lee, Jae Song, T. Kim","doi":"10.1109/ASSCC.2008.4708714","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708714","url":null,"abstract":"The trends in ecosystem and dynamics of semiconductor SoC industry in Korea are described in this paper. For the past years, the development of SoC (System on Chip) fabless industries has been phenomenal in that the total revenue of fabless companies became remarkably high and a number of major players of which the sales is about $200 million are emerging in Korea. It was mainly on the basis of multimedia SoC integration into systems like mobile phones and digital TV which have been pivotal IT growth engines in Korea. In order to sustain the continuous growth, however, SoCs need to explore the new engines to which they should be expanded, e.g., energy savings, automotives and wireless networks. The new foundry-fabless collaboration areas like high voltage analog and mixed signals/RF are presented. They strongly demand process and design collaboration, are less sensitive to market fluctuations and thereby have relatively long product lifetime and ensure continuous growth while less investment is required in comparison with logic technology.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS 90纳米CMOS中无PN发生器的0.4 pj /step 10位流水线ADC的数字背景校准
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708727
M. Taherzadeh‐Sani, A. Hamoui
{"title":"Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS","authors":"M. Taherzadeh‐Sani, A. Hamoui","doi":"10.1109/ASSCC.2008.4708727","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708727","url":null,"abstract":"In nanometer digital CMOS, the linearity of pipelined A/D converters (ADCs) is degraded by the low dc gains of the opamps. Gain-enhancement techniques significantly increase the analog-circuit design complexity at low power and low voltage. Therefore, even in medium-resolution applications, digital background calibration is attractive for designing power-efficient ADCs. A simple, yet accurate, digital background calibration technique, which does not require a pseudo-random (PN) calibration signal, is proposed to minimize the power dissipation in the digital calibration unit. It achieves the same convergence speed and accuracy as PN-based techniques in 2-path (split) pipelined ADCs. A 10-bit 44-MS/s pipelined ADC, fabricated in a standard 1.2-V 90-nm digital CMOS process, uses the proposed calibration technique to achieve a 58.7-dB SNDR for a 21.5-MHz input, with a figure-of-merit (FOM) of 0.4 pJ/step.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121628753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications 7.39mm2 76mW (1944, 972) LDPC解码器芯片，用于IEEE 802.11n应用
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708787
Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu
{"title":"A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications","authors":"Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu","doi":"10.1109/ASSCC.2008.4708787","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708787","url":null,"abstract":"This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10-6, the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm2 and 7.39 mm2, respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115677006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A low power and high performance robust digital delay locked loop against noisy environments 一种低功耗、高性能、抗噪声环境的鲁棒数字延迟锁定环
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708773
Hyun-Woo Lee, Won-Joo Yun, Jong-Jin Lee, Ki-Han Kim, N. Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
{"title":"A low power and high performance robust digital delay locked loop against noisy environments","authors":"Hyun-Woo Lee, Won-Joo Yun, Jong-Jin Lee, Ki-Han Kim, N. Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung","doi":"10.1109/ASSCC.2008.4708773","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708773","url":null,"abstract":"A new low power and high performance robust digital delay locked loop is presented. The DLL has dual loops with single replica block, different-type dual DCC at input and output, replay mode function, rising edge scanner and self-calibrated power down controller (SCPDC) for stable power management. The digital DLL used for multi-Gbps graphics SDRAM is fabricated using a 66 nm DRAM process technology. Experimental results show duty-corrected clock from external duty error of plusmn10%, less than 400 cycle locking time, 1.4 GHz operation frequency at 1.7 V and 1.7 GHz at 2.0 V.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129782214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A ROM based low-power multiplier 基于ROM的低功耗乘法器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708731
B. Paul, S. Fujita, M. Okajima
{"title":"A ROM based low-power multiplier","authors":"B. Paul, S. Fujita, M. Okajima","doi":"10.1109/ASSCC.2008.4708731","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708731","url":null,"abstract":"We present a ROM based 16times16 multiplier for low power applications. The design uses sixteen 4times4 ROM based multiplier blocks followed by carry save adders and a final carry select adder (all ROM based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement results in 0.18 mum CMOS process show a 40% reduction in power over the conventional carry save array multiplier when operated at its maximum frequency. The ROM based design also provides 44% less delay than the array multiplier with a minimal increase (7.7%) in power. This demonstrates the low-power operation of the ROM based multiplier also at higher frequencies.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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