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Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker 可编程起搏通道与一个完全在芯片上的LDO调节器心脏起搏器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708783
Chih-Jen Cheng, Chung-Jui Wu, Shuenn-Yuh Lee
{"title":"Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker","authors":"Chih-Jen Cheng, Chung-Jui Wu, Shuenn-Yuh Lee","doi":"10.1109/ASSCC.2008.4708783","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708783","url":null,"abstract":"A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-mum CMOS technology, consuming total power of 1.29 muW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a power-supply rejection ratio (PSRR) of -30 dB with the output ripple of 570 muVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 muA, LDO yields a line regulation that is less than 3% deviation.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121835899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An 833-MHz 132-phase multiphase clock generator with self-calibration circuits 带有自校准电路的833 mhz 132相多相时钟发生器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708821
Shih-Chun Lin, Tai-Cheng Lee
{"title":"An 833-MHz 132-phase multiphase clock generator with self-calibration circuits","authors":"Shih-Chun Lin, Tai-Cheng Lee","doi":"10.1109/ASSCC.2008.4708821","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708821","url":null,"abstract":"An 833-MHz 132-phase clock generator with self-calibrated circuits is presented. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phases is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-mum CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A low-power 0.7-V H.264 720p video decoder 低功耗0.7 v H.264 720p视频解码器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708756
D. Finchelstein, V. Sze, M. Sinangil, Y. Koken, A. Chandrakasan
{"title":"A low-power 0.7-V H.264 720p video decoder","authors":"D. Finchelstein, V. Sze, M. Sinangil, Y. Koken, A. Chandrakasan","doi":"10.1109/ASSCC.2008.4708756","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708756","url":null,"abstract":"The H.264/AVC video coding standard can deliver high compression efficiency at a cost of large complexity and power. The increasing popularity of video capture and playback on portable devices requires that the energy of the video codec be kept to a minimum. This paper proposes several architecture optimizations such as increased parallelism, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation and reduce the power of a high-definition decoder. An H.264/AVC Baseline Level 3.1 decoder ASIC was fabricated in 65 nm CMOS and verified. It operates down to 0.7-V and has a measured power of 1.8 mW when decoding a high definition 720 p video at 30 frames per second, which is over an order of magnitude lower than previously published results.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122181295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
500Mbps, 670μW/pin capacitively coupled receiver with self reset scheme for wireless connectors 500Mbps, 670μW/pin电容耦合接收器，无线连接器自复位方案
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708737
K. Ikeuchi, K. Inagaki, H. Kusamitsu, T. Ito, M. Takamiya, T. Sakurai
{"title":"500Mbps, 670μW/pin capacitively coupled receiver with self reset scheme for wireless connectors","authors":"K. Ikeuchi, K. Inagaki, H. Kusamitsu, T. Ito, M. Takamiya, T. Sakurai","doi":"10.1109/ASSCC.2008.4708737","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708737","url":null,"abstract":"Using capacitively coupled signaling, the feasibility of implementing an electronic connector as short as 240 mum in height is demonstrated for the first time using 0.18 mum CMOS technology and 125 mum FR4 printed circuit boards (PCBs). Maximum data rate of 500 Mbps/pin and 3.6 Gbps/mm2 are measured with 670 muW/pin of power consumption even with large parasitic capacitance associated with the FR4 board. Compared to the conventional circuits, the proposed self reset circuit can send signals 2.8x faster at the same parasitic capacitance or allow 6x more parasitic capacitance at the same data rate.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS 20Gb/s 1/4速率和40Gb/s 1/8速率突发模式CDR电路，0.13 μm CMOS
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708819
Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu
{"title":"20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS","authors":"Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu","doi":"10.1109/ASSCC.2008.4708819","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708819","url":null,"abstract":"In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132784308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2GHz CMOS noise cancellation VCO 2GHz CMOS降噪压控振荡器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708827
A. Bansal, C. Heng, Yuanjin Zheng
{"title":"2GHz CMOS noise cancellation VCO","authors":"A. Bansal, C. Heng, Yuanjin Zheng","doi":"10.1109/ASSCC.2008.4708827","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708827","url":null,"abstract":"A 2 GHz CMOS VCO, employing noise cancellation to eliminate flicker noise up-conversion, has been fabricated in 0.35 mum CMOS. An overall phase noise reduction of 10 dB has been measured with the proposed technique, and phase noise of -121.6 dBc/Hz@500 kHz offset has been achieved. The VCO core consumes 2.8 mA under 2.4V supply and occupies an area of 0.7 mmtimes0.8 mm. The proposed VCO measured FOM of -186 dBc/Hz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123663767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 12th order active-RC filter with automatic frequency tuning for DVB Tuner applications 用于DVB调谐器应用的具有自动频率调谐的12阶有源rc滤波器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708782
Liang Zou, Kefeng Han, Youchun Liao, Hao Min, Zhangwen Tang
{"title":"A 12th order active-RC filter with automatic frequency tuning for DVB Tuner applications","authors":"Liang Zou, Kefeng Han, Youchun Liao, Hao Min, Zhangwen Tang","doi":"10.1109/ASSCC.2008.4708782","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708782","url":null,"abstract":"A 12th order active-RC filter for DVB Tuner applications with automatic frequency tuning (AFT) is presented in this paper. The filter is implemented in Butterworth biquad structure. The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched-capacitor array. The measurement results indicate that the precision of tuning circuit can be controlled less than plusmn2.3%, the in-band group delay variation is 70 ns, and the in-band IM3 achieves -60 dB with -27 dbm input power. This proposed filter circuit, fabricated in a SMIC 0.18 mum CMOS process, consumes 6 mA current with 1.8 V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124196350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A low energy bio sensor node processor for continuous healthcare monitoring system 一种用于连续医疗监测系统的低能量生物传感器节点处理器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708791
Hyejung Kim, Yongsang Kim, H. Yoo
{"title":"A low energy bio sensor node processor for continuous healthcare monitoring system","authors":"Hyejung Kim, Yongsang Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708791","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708791","url":null,"abstract":"A low energy sensor node processor is proposed for continuous healthcare monitoring application. The bio signal processing block is integrated into the processor to support the compression and the encryption. A quadratic level bio signal compression algorithm is proposed to reduce the transmission power consumption and the memory capacity. And the AES-128 data encryption datapath is integrated for user privacy and authentication. The CR is 8.4:1, the PRD is 0.897% and the compression rate is 6.4 Mbps. The encryption rate is 1.6 Mbps and the normalized performance is 0.4b/cycle/k-gates which is the highest value compared to the related works. The proposed processor consumes 0.56 nJ/bit at 1V supply voltage with 1MHz operating frequency in 0.25-mum CMOS process.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 66fps 3 8mW nearest neighbor matching processor with hierarchical VQ algorithm for real-time object recognition 基于分层VQ算法的66fps 38mw最近邻匹配处理器用于实时目标识别
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708757
Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, H. Yoo
{"title":"A 66fps 3 8mW nearest neighbor matching processor with hierarchical VQ algorithm for real-time object recognition","authors":"Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708757","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708757","url":null,"abstract":"A 66 fps 38 mW nearest neighbor matching processor for real-time object recognition has been fabricated in 0.13 mum CMOS technology. It consists of RISC processing core, pre-fetch DMA, and two independent sets of logic merged memories. Based on hierarchical vector quantization (H-VQ) algorithm, implemented processor achieves 22.5X cycle time reduction in matching process without any accuracy loss in VQ operation. As a result, 66 fps frame rate is obtained for QVGA (320times240 pixels) video images with 5632-entry database.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A wireless capsule endoscopic system with a low-power controlling and processing ASIC 一种具有低功耗控制和处理ASIC的无线胶囊内镜系统
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708792
Xinkai Chen, Xiaoyu Zhang, Lingwei Zhang, Nan Qi, Hanjun Jiang, Zhihua Wang
{"title":"A wireless capsule endoscopic system with a low-power controlling and processing ASIC","authors":"Xinkai Chen, Xiaoyu Zhang, Lingwei Zhang, Nan Qi, Hanjun Jiang, Zhihua Wang","doi":"10.1109/ASSCC.2008.4708792","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708792","url":null,"abstract":"This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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