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A 60-GHz direct-conversion transmitter in 130-nm CMOS 一个60 ghz直接转换发射器在130纳米CMOS
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708748
F. Zhang, B. Yang, B. Wicks, Z. Liu, C. Ta, Y. Mo, K. Wang, G. Felic, P. Nadagouda, T. Walsh, W. Shieh, I. Mareels, R. Evans, E. Skafidas
{"title":"A 60-GHz direct-conversion transmitter in 130-nm CMOS","authors":"F. Zhang, B. Yang, B. Wicks, Z. Liu, C. Ta, Y. Mo, K. Wang, G. Felic, P. Nadagouda, T. Walsh, W. Shieh, I. Mareels, R. Evans, E. Skafidas","doi":"10.1109/ASSCC.2008.4708748","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708748","url":null,"abstract":"This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SiGe HBT quadrature VCO utilizing trifilar transformers
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708828
Jin-Siang Syu, C. Meng, G. Huang
{"title":"SiGe HBT quadrature VCO utilizing trifilar transformers","authors":"Jin-Siang Syu, C. Meng, G. Huang","doi":"10.1109/ASSCC.2008.4708828","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708828","url":null,"abstract":"A trifilar-coupling quadrature voltage-controlled oscillator (QVCO) is demonstrated using 0.35-mum SiGe heterojunction bipolar transistor (HBT) technology. The trifilar transformer consisting of one primary coil and two secondary coils is used in this work to separate the collector and base bias for output voltage swing optimization and also to replace a conventional transistor-coupling method for quadrature output generation, simultaneously. As a result, the trifilar-coupling QVCO achieves the 191.6-dBc/Hz FOM at the supply voltage of 1.2 V The on-chip passive single side-band (SSB) upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Consequently, the side-band rejection ratio of 37.7 dB is achieved.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122595975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1.25Gbps optical links for mobile handsets 1.25Gbps光链路用于移动手持设备
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708722
S. Azuma, Ryotatsu Yanagimoto, S. Kamitani, M. Edamoto, K. Arata, H. Matsui, H. Akada, R. Masuda, K. Hoshino, K. Nagura, H. Ogawa
{"title":"1.25Gbps optical links for mobile handsets","authors":"S. Azuma, Ryotatsu Yanagimoto, S. Kamitani, M. Edamoto, K. Arata, H. Matsui, H. Akada, R. Masuda, K. Hoshino, K. Nagura, H. Ogawa","doi":"10.1109/ASSCC.2008.4708722","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708722","url":null,"abstract":"This paper presents a 1.25 Gbps optical links design for mobile handsets. The system consists of an optical connector and a SER/DES main chip. The former contains an 850 nm VCSEL (vertical cavity surface emission laser), a GaAs-PIN photodiode and a transimpedance amplifier (TIA). The later includes a serializer, a deserializer, a VCSEL driver, a limiting amplifier, a PLL and a CDR. The chip and TIA were fabricated in a 0.13 um CMOS process with MIM capacitors. A digital type CDR with fine timing controls allows sharing a VCO between transmitter and receiver, resulting in reduced both power consumption and silicon area. The system fully demonstrated a 1.25 Gbps data and video stream transmission, consuming 108.4 mW of power under 1.2 V/3.3 V supply voltages.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 65 fJ/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3D system integration 基于电荷回收技术的65fj /b电感耦合片间收发器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708738
K. Niitsu, S. Kawai, N. Miura, H. Ishikuro, T. Kuroda
{"title":"A 65 fJ/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3D system integration","authors":"K. Niitsu, S. Kawai, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2008.4708738","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708738","url":null,"abstract":"This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90 nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading any of timing margin, data rate and bit error rate.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121452195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 1.2V interference-sturdiness, DC-offset calibrated CMOS receiver utilizing a current-mode filter for UWB 一个1.2V抗干扰，直流偏置校准CMOS接收器，利用电流模式滤波器用于超宽带
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708798
Horng-Yuan Shih, Wei-Hsien Chen, K. Juang, Tzu-Yi Yang, C. Kuo
{"title":"A 1.2V interference-sturdiness, DC-offset calibrated CMOS receiver utilizing a current-mode filter for UWB","authors":"Horng-Yuan Shih, Wei-Hsien Chen, K. Juang, Tzu-Yi Yang, C. Kuo","doi":"10.1109/ASSCC.2008.4708798","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708798","url":null,"abstract":"An interference-sturdiness receiver with a current-mode filter for 3-5 GHz UWB applications is implemented in a 1.2V 0.13 mum CMOS process. The chip provides a maximum voltage gain of 70 dB and a dynamic range of 60 dB. The measured in-band OIP3 is +9.39 dBm, out-of-band IIP3 -15 dBm and noise figure 6.8 dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 770-MHz, 70-mW, 8-bit subranging ADC using reference voltage precharging architecture 采用参考电压预充电架构的770-MHz, 70-mW, 8位分频ADC
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708724
K. Ohhata, K. Uchino, Y. Shimizu, Y. Oyama, K. Yamashita
{"title":"A 770-MHz, 70-mW, 8-bit subranging ADC using reference voltage precharging architecture","authors":"K. Ohhata, K. Uchino, Y. Shimizu, Y. Oyama, K. Yamashita","doi":"10.1109/ASSCC.2008.4708724","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708724","url":null,"abstract":"This paper describes a high-speed low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with body-bias control circuit is employed to reduce the distortion at high sampling rate. The test chip fabricated using 90-nm CMOS technology shows a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133793729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design considerations for low-power high-performance mobile logic and memory interfaces 低功耗高性能移动逻辑和内存接口的设计注意事项
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708764
R. Palmer, J. Poulton, A. Fuller, J. Chen, J. Zerbe
{"title":"Design considerations for low-power high-performance mobile logic and memory interfaces","authors":"R. Palmer, J. Poulton, A. Fuller, J. Chen, J. Zerbe","doi":"10.1109/ASSCC.2008.4708764","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708764","url":null,"abstract":"This paper highlights design considerations for low-power, high-performance mobile memory and logic interfaces, based on the results from the 14 mW, 6.25 Gb/s transceiver test chip demonstrated in 90 nm CMOS. One of the keys to achieving 2.25 mW/Gbps was the highly-sensitive, low-offset receiver. An accurate receiver enables low-swing signaling and requires less power and area from the transmitter. The smaller transceiver design in turn lowers the clock distribution power and improves the signal quality by presenting less loading to the clock and the channel, respectively. The improved signal quality enables even lower signal swing and a ldquospiral of goodnessrdquo continues. This paper examines these aspects in detail and discusses their potential implications to a broad spectrum of future low-power, high-performance mobile interface designs.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design of energy efficient 10ps per bit adder circuits in CMOS CMOS中10ps / bit高能效加法器电路的设计
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708735
V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi
{"title":"Design of energy efficient 10ps per bit adder circuits in CMOS","authors":"V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/ASSCC.2008.4708735","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708735","url":null,"abstract":"This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family-feedthrough logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127725627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A two-electrode 2.88nJ/conversion biopotential acquisition system for portable healthcare device 便携式医疗器械用双电极2.88nJ/转换生物电位采集系统
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708794
Long Yan, Namjun Cho, J. Yoo, Binhee Kim, H. Yoo
{"title":"A two-electrode 2.88nJ/conversion biopotential acquisition system for portable healthcare device","authors":"Long Yan, Namjun Cho, J. Yoo, Binhee Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708794","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708794","url":null,"abstract":"A 2.88 nJ/Conversion low energy biopotential acquisition system is designed for portable healthcare device. Two dry copper contact electrodes with 1.2-cm diameter are used to easily interface between skin and healthcare device. Chopping technique is adopted at readout front end to obtain thermal noise floor of 1.3 uVrms over 0.5~200 Hz and CMRR over 100 dB to mitigate common-mode body potential induced from AC power line. A 4-stage gain control and band selection blocks are integrated to digitally calibrate for different types of biomedical signal and an 8-bit synchronous successive approximation register (SAR) A/D is used to digitize sensed biopotentials. A test chip is implemented in 0.18 um, 1.8 V supply CMOS technology and successively verified by readout ECG signal with two electrodes contact at chest of body with separating 6 cm.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115939292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Cell Broadband Engine performance and yield benchmark in 65nm SOI CMOS with spatial, temporal and parametric process variability model 基于空间、时间和参数制程可变性模型的65nm SOI CMOS电池宽带引擎性能和良率基准
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708719
Choongyeun Cho, D.D. Kim, Jonghae Kim
{"title":"Cell Broadband Engine performance and yield benchmark in 65nm SOI CMOS with spatial, temporal and parametric process variability model","authors":"Choongyeun Cho, D.D. Kim, Jonghae Kim","doi":"10.1109/ASSCC.2008.4708719","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708719","url":null,"abstract":"This paper introduces a process variability model to determine the performance and yield of the cell broadband engine (CBE) in 65 nm SOI CMOS. The model incorporates spatial (die-to-die), temporal (manufacturing process drift), and parametric dimensions, and provides microprocessor performance tracking and comprehensive view on the process variability with embedded ring oscillator measurement at the wafer level. It extracts CBE performance regularity within die for the circuit design and models, and reveals the semiconductor manufacturing signatures in wafers and lots for process technology. The model reduces performance estimation testing requirements by surpassing conventional methodspsila accuracy by 28%.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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