A 770-MHz, 70-mW, 8-bit subranging ADC using reference voltage precharging architecture

Abstract

This paper describes a high-speed low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with body-bias control circuit is employed to reduce the distortion at high sampling rate. The test chip fabricated using 90-nm CMOS technology shows a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.