{"title":"20Gb/s 1/4速率和40Gb/s 1/8速率突发模式CDR电路，0.13 μm CMOS","authors":"Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu","doi":"10.1109/ASSCC.2008.4708819","DOIUrl":null,"url":null,"abstract":"In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS\",\"authors\":\"Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu\",\"doi\":\"10.1109/ASSCC.2008.4708819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708819\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS
In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.
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