An 833-MHz 132-phase multiphase clock generator with self-calibration circuits

Shih-Chun Lin, Tai-Cheng Lee
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引用次数: 9

Abstract

An 833-MHz 132-phase clock generator with self-calibrated circuits is presented. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phases is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-mum CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply.
带有自校准电路的833 mhz 132相多相时钟发生器
介绍了一种带有自校准电路的833 mhz 132相时钟发生器。由于输出相位数是两个延迟锁环的级数的乘积,因此使用两个延迟锁环有效地产生相位。提出了一种采用顺序比较法的动态链接库标定算法。校准电路只需要一个电荷泵和一个鉴相器,所有输出信号经过同一路径。因此,可以避免器件失配的影响,并且可以消除路径的失配。这种带有自校准电路的多相时钟发生器采用0.13 μ m CMOS技术制造,同时从单个1.2 v电源消耗67.2 mW。
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