A low power and high performance robust digital delay locked loop against noisy environments

Abstract

A new low power and high performance robust digital delay locked loop is presented. The DLL has dual loops with single replica block, different-type dual DCC at input and output, replay mode function, rising edge scanner and self-calibrated power down controller (SCPDC) for stable power management. The digital DLL used for multi-Gbps graphics SDRAM is fabricated using a 66 nm DRAM process technology. Experimental results show duty-corrected clock from external duty error of plusmn10%, less than 400 cycle locking time, 1.4 GHz operation frequency at 1.7 V and 1.7 GHz at 2.0 V.